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 D at a S he et , DS 4, F eb ru ar y 20 01
Q ua d LI UTM Q ua d L i ne I n te r fa c e U ni t fo r E 1 T 1J 1 P EB 22 5 04 Ve r s i o n 1. 1
Da ta c o m
Never
stop
thinking.
Edition 2001-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 Munchen, Germany
(c) Infineon Technologies AG 2/19/01. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D at a S he et , DS 4, F eb ru ar y 20 01
Q ua d LI UTM Q ua d L i ne I n te r fa c e U ni t fo r E 1 T 1J 1 P EB 22 5 04 Ve r s i o n 1. 1
Da ta c o m
Never
stop
thinking.
PEB 22504 Revision History: Previous Version: Page 7 60 99 121 100 101 2001-02 Data Sheet, DS3, 2000-09 DS4
Subjects (major changes since last revision) 5 V supply mode is not supported e-mail address changed Global Configuration Register Power Supply Range External Line Frontend Calculator Transmiter output current Receiver sensitivity
For questions on technology, delivery, and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com
PEB 22504 QuadLIU V1.1
Preface
The Quad Line Interface Unit PEB 22504 (QuadLIUTM) is a flexible line interface unit for a wide area of telecommunication and data communication applications. The device contains four complete channels on one chip to save board space and power consumption. This document provides complete reference information to configure E1, T1, and J1 applications. Organization of this Document This Data Sheet is organized as follows: * Chapter 1, Overview Gives a general description of the product and its family, lists the key features, and presents some typical applications. * Chapter 2, Pin Descriptions Lists pin locations with associated signals, categorizes signals according to function, and describes signals. * Chapter 3, Functional Description This chapter describes the functional blocks and principal operation modes. * Chapter 4, Interface Description Describes the various device interfaces. * Chapter 5, Operational Description Shows the operation modes and how they are to be initialized. * Chapter 6, Register Description Gives a detailed description of all implemented registers and how to use them in different applications/configurations. * Chapter 7, Electrical Characteristics Specifies maximum ratings, DC and AC characteristics. * Chapter 8, Package Outlines Shows the mechanical values of the device package. * Chapter 9, Appendix Gives an example for overvoltage protection and information about application notes and other support.
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* Chapter 10, Glossary * Index
Related Documentation This document refers to the following international standards (in alphabetical/numerical order): ANSI/EIA-656 ANSI T1.102 ANSI T1.231 ANSI T1.403 AT&T TR43802 AT&T TR62411 (page 119) (page 115) (page 71, page 89, page 90) (page 50, page 90) (page 40) (page 40, page 44, page 49)
ESD Ass. Standard EOS/ESD-5.1-1993 (page 98) ETSI ETS 300 011 ETSI ETS 300 233 ETSI TBR12 ETSI TBR13 FCC68 IEEE 1149.1 ITU-T G.703 ITU-T G.736-739 ITU-T G.775 ITU-T G.823 ITU-T G.824 ITU-T I.431 MIL-Std. 883D Telcordia TR-NWT-1089 TR-TSY 009 TR-TSY 253 TR-TSY 499 UL 1459 (page 40) (page 40) (page 40) (page 40) (page 39, page 40, page 89) (page 40, page 42) (page 40, page 42) (page 47) (page 33) (page 40) (page 40) (page 39, page 39, page 89, page 89) (page 40) (page 40) (page 40, page 42, page 44, page 47) (page 98)
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Your Comments We welcome your comments on this document. We are continuously trying improving our documentation. Please send your remarks and suggestions by e-mail to com.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (QuadLIUTM), device number (PEB 22504), device version (Version 1.1), and in the body of your e-mail: document type (Data Sheet), issue date (2001-02) and document revision number (DS4).
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PEB 22504 QuadLIU V1.1
Table of Contents 1 1.1 1.2 1.3 2 2.1 2.2 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 4.1.11 4.1.12 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 Page 12 13 15 16
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Clocking Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short-haul/Long-haul Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Equalization Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Line Attenuation Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Line Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse-Density Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse-Density Enforcer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Pulse Shaper and Line Build-Out . . . . . . . . . . . . . . . . . Transmit Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintenance Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . One-Second Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pseudo-Random Bit Sequence Generation and Monitor . . . . . . . . . . . . In-Band Loop Generation and Detection . . . . . . . . . . . . . . . . . . . . . . . . Remote Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
28 28 29 30 30 33 35 36 36 36 36 37 37 38 38 39 39 40 43 44 44 45 45 46 46 47 48 48 49 49 49 49 50 51
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Table of Contents 4.4.6 4.4.7 4.4.8 4.4.9 5 5.1 5.2 5.3 5.3.1 5.3.2 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.5 7.6 7.7 8 9 9.1 9.2 10 Page 52 53 54 55 56 56 56 56 56 57 59 59 60 88 89
Local Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Data Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Initialization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Description of Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Description of Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 JTAG Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Pulse Templates - Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Page
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 QuadLIU Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 QuadLIU Repeater Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . . 33 Flexible Master Clock Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Receiver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Receive Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Jitter Attenuation Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Transmitter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Transmit Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Transmit Line Monitor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Remote Loop Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Local Loop Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Digital Loop Signal FLow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Transmit Data Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . 55 MCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 JTAG Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Intel Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . 105 Intel Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Intel Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Intel Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Motorola Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Motorola Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 TCLK Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 RCLK Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 FSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 E1 Pulse Shape at Transmitter Output . . . . . . . . . . . . . . . . . . . . . . . 114 T1 Pulse Shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Thermal Behaviour of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Input/Output Waveforms for AC Testing . . . . . . . . . . . . . . . . . . . . . . 117 Master Clock Frequency Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . 120 External Line Frontend Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Page
Control Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Signal Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Boundary Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Selectable Bus and Microprocessor Interface Configuration . . . . . . . . 30 TAP Controller Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Examples of External Component Values (Receive) . . . . . . . . . . . . . . 36 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Examples of External Component Values (Transmit) . . . . . . . . . . . . . 45 Initial Values after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Initialization Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Control Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Pulse Shaper Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Clock Mode Register Settings for E1 or T1/J1 . . . . . . . . . . . . . . . . . . . 87 Status Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 MCLK Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 JTAG Boundary Scan Timing Parameter Values. . . . . . . . . . . . . . . . 104 Reset Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Intel Bus Interface Timing Parameter Values . . . . . . . . . . . . . . . . . . 107 Motorola Bus Interface Timing Parameter Values . . . . . . . . . . . . . . . 109 TCLK Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 RCLK Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SYNC Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 FSC Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 T1 Pulse Template (ANSI T1.102) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Package Characteristic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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Overview
1
Overview
The QuadLIUTM PEB 22504 Quad Line Interface Unit is a device to connect four E1/T1/ J1 framer devices to four analog or digital lines. The line interface is selectable for longhaul or short-haul applications and fulfills the relevant standards for E1, T1, and J1 systems. The QuadLIUTM comes in a high-density P-TQFP-100-3 package (SMD) to save a significant amount of board space compared to a configuration using single line-interface circuits. Crystal-less jitter attenuation with only one master clock source further reduces the amount of required external components. Equipped with a flexible microcontroller interface, it fits to any control processor environment.
Data Sheet
12
2001-02
Quad Line Interface Unit for E1T1J1 QuadLIUTM
PEB 22504
Version 1.1
CMOS
1.1
Features
* High-density generic interface for all E1/T1/J1 applications * Quad analog receive and transmit circuitry for longand short-haul applications * Clock and data recovery using an integrated digital phase-locked loop * Programmable transmit pulse shapes for E1, T1 and J1 signals
P-TQFP-100-3
* Maximum line attenuation up to -36 dB at 1024 kHz (E1) and up to -36 dB at 772 kHz (T1/J1) * Noise- and crosstalk-filter, line attenuation status * Programmable Line Build-Out for CSU signals according to ANSI T1.403 and FCC68 0dB, -7.5dB, -15dB, -22.5 dB * Low transmitter output impedances for high transmit return loss * Tristate function of the analog transmit line outputs * Transmit line monitor protecting the device from damage * Jitter specifications of ITU-T I.431 , G.703 , G.736, G.823, ETS 300011, TBR12/13 and AT&T TR62411 met * Tolerates more than 0.4 UI high frequency input jitter * Crystal-less wander and jitter attenuation/compensation * Flexible master clock frequency in the range of 1.02 to 20 MHz * Power-down function per channel * Dual- or single-rail digital inputs and outputs to the framer interface * Unipolar CMI for interfacing fiber-optical transmission routes * Selectable line codes (HDB3, B8ZS, AMI with zero code suppression) * Loss-of-signal indication with programmable thresholds according to ITU-T G.775, ETS300233, ANSI T1. 403 and T1.231 * Clock generator for jitter-free system/transmit clocks per channel * Local loop, remote loop and digital loop back for diagnostic purposes
Type PEB 22504
Data Sheet
Package P-TQFP-100-3
13 2001-02
PEB 22504 QuadLIU V1.1
Overview * * * * * * * * * Alarm and performance monitoring per second Two 16-bit counters for code violations and PRBS bit errors Insertion and extraction of Alarm Indication Signals (AIS) Elastic store for receive or transmit clock wander and jitter compensation Controlled slip capability and slip indication Programmable elastic buffer size: 256 bits/128 bits/64 bits/32 bits/bypass Programmable in-band loop code detection and generation according to TR 62411 Pseudo-Random Bit Sequence (PRBS) generator and monitor Flexible software controlled device configuration
Microprocessor Interface Mode * * * * * 8-bit microprocessor bus interface (Intel or Motorola type) All registers directly accessible Multiplexed and non-multiplexed address bus operations Hardware and software reset options One-second timer
General * * * * * Boundary scan standard IEEE 1149.1 P-TQFP-100-3 package (body size 14 mm x 14 mm) Single power supply: 3.3 V Temperature range: -40C to +85C Low power device, typical power consumption 100 mW per channel
Applications * * * * * * * * Wireless Basestations ATM and frame relay gateways CSUs, DSUs Internet access equipment LAN/WAN Router ISDN-PRI, PABX Digital Access Cross-connect Systems (DACS) SDH/SONET ADD/DROP Multiplexer
Data Sheet
14
2001-02
PEB 22504 QuadLIU V1.1
Overview
1.2
Logic Symbol
VDDR(1-4) VSSR(1-4) RL1(1-4) RL2(1-4) VDDX(1-4) VSSX(1-4) XL1(1-4) XL2(1-4) TDI TMS TCK TRS TDO
RCLK(1-4) RDOP(1-4) RDON(1-4)
TCLK(1-4) XDIP(1-4) XDIN/TRIST(1-4)
QuadLIU PEB 22504
MFP(1-4) FSC SYNC
VDD(1-5) VSS(1-5)
A(0-6) D(0-7) ALE RD/DS WR/RW CS
MCLK RES MODE
INT
F0021
Figure 1
Logic Symbol
Data Sheet
15
2001-02
PEB 22504 QuadLIU V1.1
Overview
1.3
Typical Applications
Figure 2 shows a multiple link application using the QuadLIUTM. Figure 3 shows a repeater application.
4 x E1/T1/J1 Receive & Transmit
QuadLIUTM PEB 22504
Framer ASIC
System Highway
Microprocessor
F0195
Figure 2
QuadLIU Application
Data Sheet
16
2001-02
PEB 22504 QuadLIU V1.1
Overview
RL1
RDOP RCLK
Bidirectional Line #1
RL2 XL1
RDON XDIP TCLK
XL2 RL1
XDIN 1/2 TM QuadLIU RDOP RCLK
Bidirectional Line #2
RL2 XL1
RDON XDIP TCLK
XL2
XDIN
F0069
Figure 3
QuadLIU Repeater Application
Data Sheet
17
2001-02
PEB 22504 QuadLIU V1.1
Pin Descriptions
2
2.1
Pin Descriptions
Pin Diagram
P-TQFP-100-3 (top view)
VSSX TCLK4 XDIN4/TRIST4 XDIP4 TCLK3 XDIN3/TRIST3 XDIP3 TCLK2 XDIN2/TRIST2 XDIP2 TCLK1 XDIN1/TRIST1 XDIP1 VDD VSS INT ALE A0 A1 A2 A3 A4 A5 A6 VSSX
75 76
XL1.4 VDDX XL2.4 VDDR RL1.4/ROID4 RL2.4 VSSR D7 D6 D5 D4 VSS VDD D3 D2 D1 D0 MODE VSSR RL2.3 RL1.3/ROID3 VDDR XL2.3 VDDX XL1.3
70 65 60 55 51 50 80 45 85 40
QuadLIUTM PEB 22504
90 35
95 30
100 1
5
10
15
20
26 25
VSSX RCLK4 RDON4 RDOP4 MFP4 VSS VDD RCLK3 RDON3 RDOP3 MFP3 CS WR/RW RD/DS RCLK2 RDON2 RDOP2 MFP2 VSS VDD RCLK1 RDON1 RDOP1 MFP1 VSSX
XL1.1 VDDX XL2.1 VDDR RL1.1/ROID1 RL2.1 VSSR RES FSC SYNC VDD MCLK VSS TRS TDI TMS TCK TDO VSSR RL2.2 RL1.2/ROID2 VDDR XL2.2 VDDX XL1.2
F0063
Figure 4
Data Sheet
Pin Configuration
18 2001-02
PEB 22504 QuadLIU V1.1
Pin Descriptions
2.2
Table 1 Pin No.
Pin Definitions and Functions
Control Pin Functions Signal Input (I) Output (O) Supply (S) I + PU Function
93...99
A(0:6)
Address Bus Selects one of the internal registers for read or write. Data Bus Eight-bit-wide bi-directional bus to be connected to the microprocessor data bus. Address Latch Enable A high on this line indicates an address on the external address/data bus. The address information provided on lines A(6:0) is internally latched with the falling edge of ALE. This function allows the device to be connected directly to a multiplexed address/data bus. In this case, pins A(6:0) must be connected externally to the data bus pins. In case of demultiplexed mode, this pin has to be connected to VSS or V DD directly. Chip Select A low signal selects the device for read/ write operations Read Enable/Data Strobe (Intel bus mode, MODE=low) This signal indicates a read operation. When the device is selected via CS, the RD signal enables the bus drivers to output data from an internal register addressed via A(6:0) on to Data Bus. Data Strobe (Motorola bus mode, MODE=high) This pin serves as input to control read/ write operations.
59...62 65...68 92
D(0:3) D(4:7) ALE
I/O + PU
I + PU
39
CS
I + PU
37
RD
I + PU
DS
I + PU
Data Sheet
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PEB 22504 QuadLIU V1.1
Pin Descriptions Table 1 Pin No. Control Pin Functions (cont'd) Signal Input (I) Output (O) Supply (S) I + PU Function
38
WR
WRite Enable/Read-Write Select (Intel bus mode, MODE=low) This signal indicates a write operation. When CS is active the device loads an internal register with data provided via the Data Bus. Read/Write Enable (Motorola bus mode, MODE=high) This signal distinguishes between read and write operations. INTerrupt Request General interrupt request output for all interrupt sources. These interrupt sources can be masked individually via register IMR0/1. Interrupt status is reported via register CIS (Channel Interrupt Status) and ISR0/1. Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by using register IPC.
RW
I + PU
91
INT
O/oD
Data Sheet
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PEB 22504 QuadLIU V1.1
Pin Descriptions Table 1 Pin No. Control Pin Functions (cont'd) Signal Input (I) Output (O) Supply (S) Function
27, 33, 40, 46 MFP(1:4)
Multi Function Port Depending on programming of bits LIM4.PC(2:0) this multifunction port provides different status information of the device as shown in this table below. MFP1 corresponds to channel 1, MFP4 to channel 4. O Loss-of-Signal Indication LIM4.PC(2:0) = 000 Active high, if a loss-of-signal alarm is detected. This signal corresponds directly to bit LSR0.LOS. Analog Loss-of-Signal Indication LIM4.PC(2:0) = 001 Active high, if the input level at RL1/2 drops below the programmed receive input threshold which is defined by register LIM2.RIL(2:0). PRBS Synchronization Status LIM4.PC(2:0) = 010 Active high if the Pseudo-Random Bit Sequence (PRBS) synchronization is achieved. This signal corresponds directly to bit LSR0.PRBSS. Bipolar Violation Indication LIM4.PC(2:0) = 011 Active high if a bipolar violation is detected. This signal corresponds directly to the increment signal of the code violation error counter.
LOS(1:4)
ALOS(1:4)
O
PRBSS (1:4)
O
BPV(1:4)
O
Data Sheet
21
2001-02
PEB 22504 QuadLIU V1.1
Pin Descriptions Table 1 Pin No. Control Pin Functions (cont'd) Signal Input (I) Output (O) Supply (S) O Function
27, 33, 40, 46 XLS(1:4) (cont'd)
Transmit Line Status LIM4.PC(2:0) = 100 Active high if the transmit line current limiter exceeds its maximum value. Pins XL1/2 are automatically tristated until the current drops below its maximum value ( or the "short" disappears). This signal corresponds directly to bit LSR1.XLS. Alarm Indication Signal LIM4.PC(2:0) = 101 Active high if the alarm indication signal is detected. This signal corresponds directly to bit LSR0.AIS. Clock Synchronization Reference clock for the internal DCOs of the device. Selectable via register GCR.SSF(1:0). Active high pulse input. Frame Synchronization Pulse The synchronization pulse is active low for one 2.048 (E1)/1.544 MHz (T1/J1) cycle (pulse width = 488/648 ns). FSC is derived from the jitter attenuation DCO, which must be active for FSC output (8-kHz master mode only, GCR.SSF(1:0) = 10). Active low pulse output. Transmit Line Tristate If the single-rail data stream is selected by bit LIM0.XC(1:0), a high at these pins set the appropriate XL1/2 outputs into tristate. TRISTi sets XL1.i/2.i of channel i into tristate, where i = 1 to 4.
AIS(1:4)
O
10
SYNC
I + PU
9
FSC
O
87, 84, 81, 78 TRIST(1:4)
I + PU
Data Sheet
22
2001-02
PEB 22504 QuadLIU V1.1
Pin Descriptions Table 2 Pin No. Signal Pin Functions Signal Input (I) Output (O) Supply (S) I (analog) Function
5, 21, 55, 71
RL1(1:4)
Line Receiver 1 (LIM1.ECMIR = 0, default) Analog input from the external transformer (receive bipolar ring). Receive Optical Interface Data (LIM1.ECMIR = 1) CMI data received from fiber-optical interface with 2048 (E1)/ 1544 kbit/s (T1/ J1). An internal DPLL extracts the receive route clock from the incoming data pulse. The duty cycle of the receiving signal has to be closely to 50 %. RL2 has to be connected to VSS or VDD . Line Receiver 2 (LIM1.ECMIR = 0, default) Analog input from the external transformer (receive bipolar tip). Transmit Line 1 (transmit bipolar ring) (LIM1.ECMIX = 0, default) Analog output to the external transformer. (LIM1.ECMIX = 1) Single-ail CMI output Transmit Line 2 (transmit bipolar tip) (LIM1.ECMIX = 0, default) Analog output to the external transformer. If single-rail CMI output is selected (LIM1.ECMIX = 1), this pis is undefined and has to be left open.
ROID(1:4)
I
6, 20, 56, 70
RL2(1:4)
I (analog)
1, 25, 51, 75
XL1(1:4)
O (analog)
XOID(1:4) 3, 23, 53, 73 XL2 (1:4)
O O (analog)
Data Sheet
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2001-02
PEB 22504 QuadLIU V1.1
Pin Descriptions Table 2 Pin No. Signal Pin Functions (cont'd) Signal Input (I) Output (O) Supply (S) O Function
28, 34, 41, 47 RDOP(1:4)
Receive Data Output/Positive Received data at RL1/2 is sent on RDOP/ RDON in NRZ format to the framer interface. Clocking of data is done with the rising or falling edge of RCLK(1:4), selected by bit LIM4.RPE. RDOP/RDON are set low if a loss-of-signal alarm is detected. The source of the received data is selected by bit LIM2.RD(1:0). LIM2.RD(1:0) = 00: Data recovered by the DPLL is AMI/HDB3/B8ZS decoded and output on RDOP; RDON is not defined. LIM2.RD(1:0) = 01: Dual-rail data recovered by the DPLL, not AMI/HDB3/ B8ZS decoded, is output on RDOP/RDON. LIM2.RD(1:0) = 10: Sliced data, not recovered by the DPLL is output on RDOP/ RDON. A "1" on RDOP corresponds to a positive pulse on RL1/RL2. A "1" on RDON corresponds to a negative pulse on RL1/ RL2.
29, 35, 42, 48 RDON(1:4) BPV(1:4) SCLKO SCLKI
O O O I + PU
Receive Data Output/Negative LIM1.RDON(1:0) = 00 (see above) Bipolar Violation Indication LIM1.RDON(1:0) = 01 System Clock Output LIM1.RDON(1:0) = 10 System Clock Input LIM1.RDON(1:0) = 11 Read clock for jitter attenuater buffer if internal DCO is not used (see Figure 10 on page 38).
Data Sheet
24
2001-02
PEB 22504 QuadLIU V1.1
Pin Descriptions Table 2 Pin No. Signal Pin Functions (cont'd) Signal Input (I) Output (O) Supply (S) I + PU Function
88, 85, 82, 79 XDIP(1:4)
Transmit Data In Positive Transmit data received from the framer interface is output on XL1/2. NRZ data has to be provided on XDIP. Latching of data is done with the rising or falling transitions of TCLK according to LIM4.TPE. Transmit Data In Negative If the dual-rail data stream is selected by bits LIM0.XC(1:0) transmit data received from the framer interface is output on XL1/ 2. NRZ data (AMI negative data) has to be provided on XDIN. Latching of data is done with rising or falling transitions of TCLK according to bit LIM4.TPE. Receive Clock The output functions of these ports are defined by register CMR.RS(1:0): CMR.RS(1:0) = 00: Receive Clock extracted from the incoming data pulses. CMR.RS(1:0) = 01: Receive Clock extracted from the incoming data pulses. RCLK is set high in case of loss-of-signal (LSR0.LOS=1). Selected by GCR.R1S(1:0), one of the four RCLK(1:4) is output on RCLK1. The clock frequency is 2.048 (E1)/ 1.544 MHz (T1/J1)
87, 84, 81, 78 XDIN(1:4)
I + PU
30, 36, 43, 49 RCLK(1:4)
O
SCLKO (1:4)
O
CMR.RS(1:0) = 10: Output of de-jittered system clock sourced by DCO. Clock frequency: 2.048 (E1) or 1.544 MHz (T1/J1). See Figure 10 on page 38.
Data Sheet
25
2001-02
PEB 22504 QuadLIU V1.1
Pin Descriptions Table 2 Pin No. Signal Pin Functions (cont'd) Signal Input (I) Output (O) Supply (S) I + PU Function
86, 83, 80, 77 TCLK(1:4)
Transmit Clock Input of the working clock for the transmitter with a frequency of 2.048 (E1)/ 1.544 MHz (T1/J1). Master Clock A reference clock between 1.02 MHz and 20 MHz must be provided on this pin (32 ppm accuracy). Hardware Reset A low signal on this pin forces the device into reset state. During reset, an active clock is needed on pin MCLK. Operation Mode Select 0 = Intel bus 1 = Motorola bus
12
MCLK
I
8
RES
I
58
MODE
I + PU
Data Sheet
26
2001-02
PEB 22504 QuadLIU V1.1
Pin Descriptions Table 3 Pin No. Power Supply Pins Signal Input (I) Output (O) Supply (S) S (analog) S (analog) S (analog) S (analog) S S Function
4, 22, 54, 72 7, 19, 57, 69 2, 24, 52, 74 26, 50, 76, 100 11, 31, 44, 63, 89 13, 32, 45, 64, 90
VDDR VSSR VDDX VSSX VDD VSS
Positive Power Supply for the analog receiver Power Supply Ground for the analog receiver Positive Power Supply for the analog transmitter Power Supply Ground for the analog transmitter Positive Power Supply for digital subcircuits Power Supply Ground for digital subcircuits
Table 4 Pin No.
Boundary Scan Pins Signal Input (I) Output (O) Supply (S) I + PU Function
14
TRS
Test Reset (Boundary Scan) active low; if the JTAG boundary scan is not used, this pin must be connected to RES or V SS. Test Data Input (Boundary Scan) Test Mode Select (Boundary Scan) Test Clock (Boundary Scan) Test Data Output (Boundary Scan)
15 16 17 18
TDI TMS TCK TDO
I + PU I + PU I + PU O
Note: oD = open-drain output PU = input or input/output comprising an internal pullup device To override the internal pullup by an external pulldown, a resistor value of 22 k is recommended. Unused pins containing pullups can be left open. Unused receive channels have to be connected to a fixed level (V DDR or V SSR).
Data Sheet 27 2001-02
PEB 22504 QuadLIU V1.1
Functional Description
3
3.1
Functional Description
Functional Overview
The QuadLIUTM device contains analog and digital function blocks that are configured and controlled by an external microprocessor or microcontroller. The main interfaces are * * * * * Receive-line Interface Transmit-line Interface Framer interface Microprocessor interface Boundary scan interface
as well as several control lines for reset and clocking purpose. The main internal functional blocks are * * * * * * * Analog line receiver with equalizer network and clock/data recovery Analog line driver with programmable pulse shaper and line build out Central clock-generation module Jitter attenuator in receive or transmit direction Test functions (e.g., loop switching local - remote - digital) Register access interface Boundary scan control
Data Sheet
28
2001-02
3.2
Figure 5
ALOS Detection LOS AIS Detection JATT1) Decoder
Data Sheet
RL1 / ROID
Equalizer
Block Diagram
RL2
Peak Detection Slicer
Clock & Data Recovery
RCLK RDOP RDON
Block Diagram
Digital Loop
2) 2)
Local Loop
TCLK SYNC MCLK Clocking Unit Remote Loop
IBL PRBS Generator
IBL PRBS Monitor
29
Pulse Shaper JATT1) Encoder AIS
1) JATT in receive or transmit direction alternatively
XL1 / XOID
XL2
One of four channels
2) Monitor and Generator in receive or transmit direction alternatively
Line Driver
TCLK XDIP XDIN
Transmit Line Monitor
Port Control Microprocessor Interface
Device Reset
Boundary Scan Control
CS
TDI
INT
ALE
TCK
TRS
TDO
RES
TMS
A(6:0)
D(7:0)
MODE
RD/DS
Functional Description
Common to all channels
W R/RW
PEB 22504 QuadLIU V1.1
MFP(4:1)
F0043
2001-02
PEB 22504 QuadLIU V1.1
Functional Description
3.3 3.3.1
Functional Blocks Microprocessor Control Unit
The communication between the CPU and the QuadLIUTM is done via a set of directly accessible registers. The interface may be configured as Intel or Motorola type (by control pin MODE) with a data bus width of 8 bits. The CPU transfers data to/from the QuadLIUTM, sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers. Table 5 shows how the ALE (Address Latch Enable) and MODE lines are used to control the interface type. Switching of ALE allows the QuadLIUTM to be connected directly to a multiplexed address/data bus. Table 5 ALE VSS or VDD VSS or VDD switching Selectable Bus and Microprocessor Interface Configuration MODE high low low Microprocessor interface Motorola Intel Intel Bus Structure demultiplexed demultiplexed multiplexed
3.3.1.1
Interrupt Interface
Special events in the QuadLIUTM are indicated by means of a single interrupt output, which requests the CPU to read status information from the QuadLIUTM, or to transfer data to the QuadLIUTM. The pin characteristic (open drain, push-pull) is programmable. Since only one INT request output is provided, the cause of an interrupt must be determined by the CPU by reading the QuadLIUTM's interrupt status registers CIS and ISR(1:0). The interrupt on pin INT and the interrupt status bits are reset by reading the interrupt status registers. Registers ISR0 and ISR1 are "cleared on read". The structure of the interrupt status registers is shown in Figure 6.
Data Sheet
30
2001-02
PEB 22504 QuadLIU V1.1
Functional Description
Channel Interrupt Status Register (CIS)
GIS4
GIS3 GIS2
GIS1
CH4: ISR0 / ISR1 CH4: IMR0 / IMR1
CH1: ISR0 / ISR1 CH1: IMR0 / IMR1
CH3: ISR0 / ISR1 CH3: IMR0 / IMR1
CH2: ISR0 / ISR1 CH2: IMR0 / IMR1 F0042
Figure 6
Interrupt Status Registers
Each interrupt indication of register ISR0 and ISR1 can be masked selectively by setting the corresponding bit in the mask registers IMR0 and IMR1. If the interrupt status bits are masked, they neither generate an interrupt on pin INT nor are they visible in ISR(1:0). The non-maskable Channel Interrupt Status (CIS) register serves as a pointer to pending ISRs. After the QuadLIUTM has requested an interrupt by activating its INT pin, the CPU should first read the CIS register to identify the requesting channel by bit GISx (Global Interrupt Status bit of channel x) After that the corresponding interrupt status register ISR(1:0) of the requesting channel should be examined. After reading the interrupt status registers ISR(1:0), the pointer in CIS is cleared or updated if another interrupt requires service. If all pending interrupts are acknowledged by reading the ISRs, CIS is reset and pin INT goes inactive. Updating of ISR(1:0) and CIS is prohibited only during read access. Masked Interrupts Visible in Status Registers The CIS register indicates those channels with active interrupt indications. An additional mode ("visible mode") may be selected via bit LIM4.VIS. In this mode, masked interrupt status bits neither generate an interrupt on pin INT nor are they visible in CIS, but are displayed in the corresponding ISR(s) ISR(1:0). This mode is useful when some interrupt status bits are to be polled in the individual ISRs.
Data Sheet
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PEB 22504 QuadLIU V1.1
Functional Description
Note: In the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. Thus, when polling of some interrupt status bits is desired, care must be taken that unmasked interrupts are not lost in the process. All unmasked interrupt statuses are treated as in normal mode.
Please note that whenever polling is used, all interrupt status registers concerned have to be polled individually (no "hierarchical" polling is possible), since CIS contains information on only those interrupts that were actually generated, i.e., unmasked interrupts.
Data Sheet
32
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PEB 22504 QuadLIU V1.1
Functional Description
3.3.2
Boundary Scan Unit
In the QuadLIUTM a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and boundary scan, meet the requirements in the JTAG standard IEEE 1149.1. Figure 7 gives an overview.
TAP controller reset TRS
clock TCK
Clock Generation Reset
test control TMS
BD data in
Identification Register (32 bits)
1 2
data in TDI
TAP Controller finite state machine instruction register test signal generator
control bus
enable TDO data out
Figure 7
Boundary Scan (n bits)
n F0115
ID data out BD data out
Block Diagram of Test Access Port and Boundary Scan
After switching on the device (power-on), a reset signal has to be applied to TRS, which forces the TAP controller into test logic reset state. For normal operation without boundary scan access, the boundary reset pin TRS can be tied to the device reset pin RES. The boundary length is 150.
Data Sheet
33
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PEB 22504 QuadLIU V1.1
Functional Description If no boundary scan operation is used, TRS has to be connected to RST or VSS. TMS, TCK and TDI do not need to be connected since pullup transistors ensure high input levels in this case. Test handling (boundary scan operation) is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, that means TRS is connected to VDD or it remains unconnected due to its internal pull up. Test data at TDI is loaded with a clock signal connected to TCK. "1" or "0" on TMS causes a transition from one controller state to another; constant "1" on TMS leads to normal operation of the chip. An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out and enable) and an I/O-pin (I/O) uses three cells (data in, data out and enable). Note that most functional output and input pins of the QuadLIUTM are tested as I/O pins in boundary scan, hence using three cells. The desired test mode is selected by serially loading a 8-bit instruction code into the instruction register via TDI (LSB first). EXTEST is used to examine the interconnection of the devices on the board. In this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values ("0" or "1"). Then the contents of the boundary scan is shifted to TDO. At the same time the next scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. SAMPLE is a test mode which provides a snapshot of pin levels during normal operation. IDCODE: A 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to "1". The ID code field is set to: 0001 0000 0000 0101 1010 0000 1000 0011 Version = 1H, Part Number = 005AH, Manufacturer = 083H (including LSB, fixed to "1") BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle. An alphabetical overview of all TAP controller operation codes is given in Table 6. Table 6 BYPASS EXTEST IDCODE SAMPLE reserved for device test TAP Controller Instruction Codes Instruction Code 11111111 00000000 00000100 00000001 01010011
TAP Instruction
Data Sheet
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PEB 22504 QuadLIU V1.1
Functional Description
3.3.3
Master Clocking Unit
The QuadLIUTM provides a flexible clocking unit that can use a stable reference clock in the range of 1.02 MHz to 20 MHz supplied on pin MCLK. The clocking unit has to be tuned to the selected reference frequency by setting the Global Clock Mode registers (GCM(6:1)) accordingly. The calculation formulas for the appropriate register settings can be found in Chapter 6.2 on page 87. All required clocks for E1 and T1/J1 operation are generated internally by this circuit. The global setting depends only on the selected master clock frequency, and is the same for E1 and T1/J1 because both clock rates are provided simultaneously. The flexible master clock unit can be disabled (GCM2.VFREQ_EN = 0, which is the default configuration after hardware reset). In this case, a fixed reference clock of 2.048 MHz (E1) or 1.544 MHz (T1/J1) has to be supplied on pin MCLK.
Note: E1 or T1/J1 mode can be selected independently for each channel if flexible clocking is selected (GCM2.VFREQ_EN = 1).
To meet the transmit clock and data accuracy requirements of E1/T1 in free running mode, the MCLK reference clock itself must have an accuracy of 32 ppm. The synthesized clock can be controlled on pin RCLK.
.
E1 Clocks MCLK Flexible Master Clock Unit T1/J1 Clocks
GCM1 - GCM6
FL0002
Figure 8
Flexible Master Clock Unit
Data Sheet
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PEB 22504 QuadLIU V1.1
Interface Description
4
4.1
Interface Description
Receiver
RL1 Line
t2
t1
R1
RL2
QuadLIU
ITS10571
Figure 9 Table 7 Parameter
Receiver Configuration Examples of External Component Values (Receive) Characteristic Impedance [] E1 75 120 120 1:1 T1 100 100 1:1 J1 110 110 1:1
R1 ( 1 %) [] 75 t2 : t1 1:1 4.1.1 Receive Line Interface
Several data input types are supported: * Ternary coded signals received at multifunction ports RL1 and RL2 from a - 10 dB or -36 dB (E1)/-36 dB (T1/J1) ternary interface. The ternary interface is selected if LIM1.ECMIR is reset. * CMI coded data on port ROID received from a fiber-optical interface. The optical interface is selected if LIM1.ECMIR is set. The signal at the ternary interface is received on both ends of a transformer. The line termination impedance 75 /120 /100 is selectable by switching resistors in parallel. This selection does not require a change of transformers.
4.1.2
Short-haul/Long-haul Interface
The QuadLIUTM has an integrated short- and long-haul line interface consisting of a receive equalization network and noise filtering.
Data Sheet
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2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.1.3
Receive Equalization Network
The QuadLIUTM automatically recovers the signals received on pins RL1/2 in a range of up to -36 dB. The maximum reachable length with a 22 AWG twisted-pair cable is 6000 feet (T1/J1). After reset the QuadLIUTM is in short-haul mode, and received signals are recovered up to a cable attenuation of -10 dB. Switching to long-haul mode is done by setting of register bit LIM1.EQON. Noise filters eliminate the higher frequency part of the received signals. The incoming data is peak-detected and sliced at 45, 50, 55, or 67% of the peak value (programmable in four steps by LIM2.SLT(1:0)) to produce the digital data stream. The received data is then forwarded to the clock and data recovery unit (DPLL) or optionally transferred to ports RDOP/RDON directly (see LIM2.RD(1:0)). The current equalizer status is indicated by register RES (Receive Equalizer Status).
4.1.4
Receive Line Attenuation Indication
RES reports the current receive line attenuation in 25 steps of approximately 1.7 dB (E1)/ 1.4 dB (T1/J1) each. The least significant five bits of this register indicate the cable attenuation in dB. These five bits are only valid together with the most significant two bits (RES.EV(1:0) = 01) .
Data Sheet
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2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.1.5
Receive Clock and Data Recovery
The analog received signal on port RL1/2 is equalized and then peak-detected to produce a digital signal. The receive clock and data recovery subcircuit extracts the route clock RCLK from the data stream received on the RL1/2 or ROID lines, and converts the data stream into a dual-rail bit stream. The clock and data recovery works with the internally generated high-frequency clock based on MCLK. Normally, the clock that is output on pin RCLK is the recovered clock from the signal provided on RL1/2, and has a duty cycle close to 50 %. The free run frequency is defined by the master clock setting [2.048 MHz (E1)/1.544 MHz (T1/J1)] in periods with no signal. The intrinsic jitter generated in the absence of any input jitter is not more than 0.02 UI (Unit Intervals).
RL1 Equalizer RL2 RCLK Slicer DPLL JATT Decoder
RDOP NRZ data BPV RDON/BPV/ SCLKO/ SCLKI SCLKI RCLK of 3 other channels SCLKO LOS RCLK2 RCLK3 RCLK4
RCLK2...4
MCLK DCO SYNC
RCLK1
F0065
Figure 10
Receive Clock System
4.1.6
Receive Line Coding
In E1 applications, HDB3 and AMI coding is provided for the data received from the ternary interface. In T1 mode, B8ZS and AMI code is supported. In case of the optical interface, CMI Code (1T2B) with HDB3/B8ZS postprocessing is provided. If the DPLL is not bypassed, the receive route clock is recovered from the data stream. The CMI decoder does not correct any errors. The HDB3 code is used along with double violation detection or extended code violation detection (optional, see LIM0.EXZE). In B8ZS or AMI, code all code violations are detected. Detected errors increment the code violation counter (16 bits length).
Data Sheet
38
2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.1.7
Pulse-Density Detector
Pulse-density violations of the received signal are detected according to ANSI T1.403. Violations are indicated (LSR0.PDEN, ISR0.PDENI) if the incoming signal contains: * More than 15 consecutive zeros or * Fewer than N ones in each and every time window of 8 x (N+1) digit time slots with N taking on all values of 1 to 23. The indication is cleared, if the pulse-density fulfills the requirement within 23 received ones.
4.1.8
Alarm Handling
The receive line interface includes alarm detection for AIS (Alarm Indication Signal) and LOS (Loss Of Signal).
4.1.8.1
AIS (Blue Alarm) Detection
The AIS is detected according to ITU-T G.775 and ANSI T1.231. In E1 applications, the alarm is set when the incoming signal has fewer than three zeros in each of two consecutive 512-bit periods. In T1 applications, the AIS alarm is set when fewer than 6 zeros are detected within a time interval of 3 ms received on RL1/2. AIS detection also works in the presence of a bit error rate of up to 10-3. An AIS alarm is indicated in a Line Status Register (LSR0.AIS) and an Interrupt Status Register (ISR0.AIS).
4.1.8.2
LOS (Red Alarm) Detection
There are different definitions for detecting LOS alarms in the ITU-T G.775, ETS 300233, ANSI T1.403 and T1.231. The QuadLIUTM covers all these standards. The LOS indication is performed by generating an interrupt (if not masked) and activating a status bit. Additionally, a LOS status change interrupt is programmable via register LIM4.SCI. * Detection: In digital receive interface mode (LIM1.ECMIR = 1), an alarm is generated if the incoming data stream has no pulses (no transitions) for a certain number (N) of consecutive pulse periods. "No pulse" means a logical zero on pin ROID. In analog receive interface mode (LIM1.ECMIR = 0), a pulse with an amplitude less than Q dB below nominal is the criteria for "no pulse". The receive signal level Q is programmable via three control bits, LIM2.RIL(2:0), related to the differential voltage between pins RL1 and RL2 (see DC Characteristics on page 100). The number N can be set via an 8-bit register, PCD. The contents of the PCD register is multiplied by 16; the product equals the number of pulse periods until the alarm has to be detected (16
Data Sheet 39 2001-02
PEB 22504 QuadLIU V1.1
Interface Description to 4096 pulse periods). ETS 300233, which requires detection intervals of at least 1 ms, can be fulfilled. * Recovery: The recovery procedure starts after detection of a logical "one" (digital receive interface) or a pulse (analog receive interface) with an amplitude more than Q dB (defined by LIM2.RIL(2:0)) of the nominal pulse. The value in the 8 bit register PCR defines the number of pulses (1 to 255) required to clear the LOS alarm. Additional recovery conditions may be programmed by register LIM5.LOSR(1:0).
4.1.9
Jitter Attenuator
The internal PLL (Phase-Locked Loop) circuitry called DCO (Digitally Controlled Oscillator) generates a "jitter-free" output clock which is directly depending on the phase difference between the incoming clock and the jitter-attenuated clock. The jitter attenuator can be placed on the receive or transmit path of each channel individually. The working clock is an internally generated high-frequency clock based on the clock provided on pin MCLK. The jitter attenuator meets the requirements of ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/13, AT&T TR62411, AT&T TR43802, TR-TSY 009, TR-TSY 253 and TR-TSY 499. The receive jitter attenuator can be synchronized either to the extracted receive clock RCLK, or to a 2.048 (E1)/1.544 MHz (T1/J1)/8 KHz (E1/T1/J1) clock provided on pin SYNC. The transmit jitter attenuator synchronizes with either the clock provided on pin TCLK, or the receive clock RCLK (remote loop/loop-timed). Received data is written into the elastic buffer with RCLK and is read out with the dejittered clock sourced by DCO (if JATT in receive direction is selected). The jitter attenuated clock can be output on pin RCLK. An 8-kHz clock is provided on pin FSC. Transmit data is written into the elastic buffer with TCLK and is read out with the dejittered clock sourced by DCO (if JATT in transmit direction is selected). In the loop-timed clock configuration (CMR.ELT) the DCO circuitry generates a transmit clock that is frequency synchronized to RCLK. The DCO circuitry attenuates the incoming jittered clock starting at 2 Hz (E1)/6 Hz (T1J1) jitter frequency with 20 dB/decade fall-off. Wander with a jitter frequency below 2/6 Hz is passed unattenuated. The intrinsic jitter in the absence of any input jitter is less than 0.02 UI. The DCO accepts gapped clocks, which are used in ATM or SDH/SONET applications. For some applications, it might be useful to start jitter attenuation at lower frequencies. Therefore the corner frequency is switchable by the factor of ten down to 0.2/0.6 Hz (CMR.SCF).
Data Sheet
40
2001-02
PEB 22504 QuadLIU V1.1
Interface Description The jitter attenuator works in two different modes: * Slave mode In slave mode (CMR.MAS = 0), the DCO is synchronized with the recovered route clock. In case of LOS (receive mode) or transmit clock is lost (transmit mode, bit LSR1.TCS = 1), the DCO switches to master mode automatically. If bit CMR.DCS is set, automatic switching from RCLK/TCLK to SYNC is disabled. * Master mode In master mode (CMR.MAS = 1) the jitter attenuator is in free-running mode if no clock is supplied on pin SYNC . If there is a clock with a frequency of 2.048 (E1)/1.544 MHz (T1/J1)/8 kHz (E1/T1/J1) on the SYNC input, the DCO is synchronized with this input signal. In some applications, it might be useful to synchronize to a gapped clock sourced by pin SYNC. In this case, the DCO circuitry would be centered to the nominal frequency. Optionally the QuadLIUTM offers the ability to disable the centering the DCO circuitry (LIM4.DCF = 1). Table 8 shows the clock modes with the corresponding synchronization sources. Table 8 Mode Clocking Modes SYNC Internal LOS active Input or TCS set no no no no VDD DCO1) Output Clock
Master Master Master Master
Free-running (DCO centered)
1.544 MHz Synchronized with SYNC input 2) GCR.SSF(1:0) = 01 2.048 MHz Synchronized with SYNC input 2) GCR.SSF(1:0) = 00 8 kHz Synchronized with SYNC input GCR.SSF(1:0) = 10 Synchronized with line RCLK/TCLK(4:1), selected by CMR.DSS(1:0)
Slave Slave Slave Slave
no no no yes
VDD
1.544 MHz Synchronized with line RCLK/TCLK(4:1), selected by CMR.DSS(1:0) 2) 2.048 MHz Synchronized with line RCLK/TCLK(4:1) , selected by CMR.DSS(1:0) 2) VDD Free running (DCO centered)
Data Sheet
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2001-02
PEB 22504 QuadLIU V1.1
Interface Description Table 8 Mode Clocking Modes (cont'd) SYNC Internal LOS active Input or TCS set yes yes DCO1) Output Clock
Slave Slave
1) 2)
1.544 MHz Synchronized with SYNC input 2) GCR.SSF(1:0) = 01 2.048 MHz Synchronized with SYNC input 2) GCR.SSF(1:0) = 00
The DCO can be used either in receive or transmit direction (see Figure 10 and Figure 14) If flexible clocking mode is selected (GCM2.VFREQ_EN = 1), the SYNC frequency can be selected independent of E1 or T1/J1 mode.
The jitter attenuator meets the jitter transfer requirements of ITU-T I.431 and G.735-739 (refer to Figure 11).
10 dB 0 -10
Attenuation
ITD10570
ITU G.736 Template LIU
-20 -30 -40 -50 -60
1
10
100
1000 Frequency
10000
Hz 100000
Figure 11
Jitter Attenuation Performance
Also the requirements of ETSI TBR12/13 are satisfied. The DCO starts jitter attenuation at about 2 Hz to ensure adequate margin against TBR12/13 output jitter limit with 15 UI input at 20 Hz.
Data Sheet
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2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.1.10
Jitter Tolerance
The QuadLIUTM receiver's tolerance to input jitter complies with ITU for CEPT applications. Figure 12 shows the curves of different input jitter specifications as well as the QuadLIUTM performance.
1000 AT&T TR 62411 TR-NWT 000499 Cat II ITU-T G.823 ITU-T I.431 QuadLIU
UI
100
Jitter Amplitude
10
1
0.1 1 10 100 1000 10000 Hz 100000
F0052
Jitter Frequency
Figure 12
Jitter Tolerance
Data Sheet
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2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.1.11
Output Jitter
In the absence of any input jitter, the QuadLIUTM generates the output jitter as specified in Table 9. Table 9 Specification AT&T TR62411 Output Jitter Measurement Filter Bandwidth Lower Cutoff 10 Hz 8 kHz 10 Hz ITU-T I.431 20 Hz 700 Hz Upper Cutoff 8 kHz 40 kHz 40 kHz 100 kHz 100 kHz Broadband Output Jitter (UI peak to peak) < 0.015 < 0.015 < 0.015 < 0.015 < 0.015 < 0.02
4.1.12
Elastic Buffer
The elastic buffer can be placed in receive or transmit direction to generate a "jitter-free" data stream. Different buffer sizes can be programmed by LOOP.BS(1:0): * * * * 00: 01: 10: 11: 256 bits 128 bits 64 bits 32 bits
Slips are performed in all buffer modes. After a slip is detected, the read pointer is adjusted to one half of the current buffer size. A slip condition is detected when the write pointer and the read pointer of the memory are nearly coincident. If a slip condition is detected, a negative slip or a positive slip is performed. For a negative slip, one half of the current buffer size is skipped. For a positive slip, one half of the current buffer size is read out twice. A positive or negative slip is indicated in the interrupt status bits ISR0.SLP and ISR0.SLN. When bit CMDR.CEB is set, the data delay through the elastic buffer is set to half of the current buffer size.
Data Sheet
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2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.2
Transmitter
The serial bit stream is then processed by the transmitter which has the following functions: * * * * AIS generation (Alarm Indication Signal) Generation of AMI, B8ZS, HDB3 or CMI coded signals Generation of IBL (In-Band Loop) code Generation of PRBS (Pseudo-Random Binary Sequence)
4.2.1
Transmit Line Interface
The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return-to-zero signals of the appropriate programmable pulse shape. The unipolar data is provided by the digital transmitter.
R1
XL1 Line
t1
t2 R1
XL2
QuadLIU
ITS10568
Figure 13 Table 10 Parameter
Transmitter Configuration Examples of External Component Values (Transmit) Characteristic Impedance [] E1 75 120 7.5 1 : 2.4 1 T1 100 2 1 : 2.4 1 J1 110 2 1 : 2.4 1
R1 ( 1 %) []
t2 : t1 XPM2.XLHC
7.5 1 : 2.4 1
Data Sheet
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2001-02
PEB 22504 QuadLIU V1.1
Interface Description In transmit direction, only the ternary or CMI interface is supported: * Ternary signal The received data stream on pins XDIP or XDIP/N is converted into a ternary signal which is output on pins XL1 and XL2. In E1 mode the HDB3 and AMI line code is employed. In T1 mode, B8ZS and AMI with or without zero code suppression is supported (selected by LIM0.XC(1:0); the encoder can also be disabled). * CMI signal The received data stream is converted into a CMI signal with HDB3 (E1) or B8ZS (T1/ J1) precoding.
4.2.2
Transmit Clock System
XL1 XL2
Line Driver
Pulse Shaper
JATT
Encoder
XDIP
XDIN
SYNC MCLK RCLK SYNC SCLKI TCLK DCO TCLK of 3 other channels
F0066
Figure 14
Transmit Clock System
The jitter attenuator can be placed in the receive or transmit path. If placed in the transmit path, data is clocked into the JATT buffer with the transmit clock TCLK. If automatic clock-switching is enabled (LIM5.ACS = 1), TCLK is replaced by the SYNC clock automatically, if TCLK is missing. The active edge of TCLK (or SYNC, if TCLK is missing) can be programmed by LIM4.TPE.
4.2.3
Pulse-Density Enforcer
The integrated pulse-density enforcer can be activated (LIM0.PDE = 1) to ensure the outgoing signal fulfills the pulse-density requirements of ANSI T1.403: * No more than 15 consecutive zeros * At least N ones in every time window of 8 x (N+1) digit time slots, with N taking on all values of 1 to 23.
Data Sheet 46 2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.2.4
Programmable Pulse Shaper and Line Build-Out
In long-haul applications, the transmit pulse masks are optionally generated according to FCC68 and ANSI T1.403 for T1 applications. To reduce the crosstalk on the received signals, the QuadLIUTM can place a transmit attenuator in the data path (LBO, Line Build Out). Transmit attenuation is selectable to be 0 , -7.5, -15 or -22.5 dB (selected by register LIM3.LBO(2:1)). ANSI T1.403 defines only 0 to -15 dB (T1/J1 mode only). The QuadLIUTM includes a programmable pulse shaper to satisfy the requirements of ITU-T I.431 , ANSI T1. 102, and various DS1, DSX-1 specifications are met. The amplitude of the pulse shaper is programmable individually via the microprocessor interface to allow a large number of different pulse templates. Adaption to the line length is selected by programming the registers XPM(2:0) as shown on page 77. To reduce power consumption, the output stage biasing can be reduced (LIM5.XLB = 1). This leads to slightly reduced slopes.
Data Sheet
47
2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.2.5
Transmit Line Monitor
The transmit line monitor compares the transmit line current on XL1 and XL2 with an onchip transmit line current limiter. The monitor detects faults on the primary side of the transformer indicated by a highly-increased transmit line current (more than about 120 mA for at least three "1" pulses), and protects the device from damage by automatically setting the transmit line driver XL1/2 in a high-impedance state. The current limiter checks the actual current value of XL1/2, and if the transmit line current drops below the detection limit, the high-impedance state is cleared. Two conditions are detected by the monitor: transmit line ones density (more than 31 consecutive zeros) indicated by LSR1.XLO and transmit line high currrent indicated by LSR1.XLS. In both cases a transmit line monitor status change interrupt is provided. The transmit line monitor function can be disabled by LIM5.XLM = 0 to reduce power consumption.
Line Monitor TRI XL1 XL2 Pulse Shaper
XDATA
ITS10936
Figure 15
Transmit Line Monitor Configuration
4.3
Framer Interface
The system side interface to the receive framer interface is realized by RDOP, RDON and RCLK. Data on RDOP/N is clocked with either the rising or falling edge of RCLK (LIM4.RPE, see Figure 10 on page 38). Data from the framer interface is sampled at XDIP and XDIN on the active edge of TCLK. The active edge can be the rising or falling edge of TCLK (LIM4.TPE). An automatic clock-switching mode can be enabled (LIM5.ACS = 1) to switch automatically to the clock provided on pin SYNC if TCLK is missing. The selected edge (risingfalling) also applies to SYNC, if selected by automatic switching.
Data Sheet
48
2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.4 4.4.1
Maintenance Functions Error Counter
The QuadLIUTM offers two error counters. Each of them is 16 bits long. They record code violations and PRBS errors. Both error counters are buffered. Updating of the buffer is done in two modes: * Every one-second interval * On demand via handshake by writing to register CMDR In the one-second-mode an internal/external one-second timer updates these buffers and resets the counter to accumulating the error events. The error counter cannot overflow. Error events occuring during reset don't get lost.
4.4.2
One-Second Timer
A one-second timer interrupt can be generated per channel internally to indicate that the enabled alarm status bits or the error counters have to be checked. The one-second timer is part of the monitor block and is related to the selected clock source (RCLK, SCLKO, SCLKI or TCLK).
4.4.3
Pseudo-Random Bit Sequence Generation and Monitor
The QuadLIUTM has the ability to generate and monitor a 215-1 or 2 20-1 PRBS with maximum zero restriction according to ITU-T O.151 and AT&T TR62411. The generated PRBS pattern is transmitted directly or inverted. The PRBS monitor senses the PRBS pattern in the receive or transmit data stream. Synchronization is done with inverted and non-inverted PRBS patterns. The current synchronization status is reported in status and interrupt status registers. Data streams consisting of continuous ones or zeros also lead to the indication of synchronous state. Each PRBS bit error increments the PRBS error counter (BECL/H). Synchronization is reached within 400 ms at a probability of 99.9 % in the presence of a bit error rate of 10 -1.
Data Sheet
49
2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.4.4
In-Band Loop Generation and Detection
The QuadLIUTM generates an unframed IBL (In-Band Loop) pattern and detects a framed or unframed IBL pattern according to ANSI T1. 403. The detection works even in the presence of bit errors at a rate of up to 10-2. The loop-up and loop-down patterns are programmable individually from 2 to 8 bits in length (LCR1.LAC(1:0) and LCR1.LDC(1:0)). Programming of loop codes is done in registers LCR2 and LCR3, using default values 00001 for activation and 001 for deactivation of the loop. The in-band loop generator and monitor can be placed either on the receive or transmit path independently (LIM3.GTP, LIM3.MTP). The monitor is enabled by setting LIM3.EPRM = 1. If the in-band loop code has been detected for at least 5 s, the QuadLIUTM optionally switches the remote loop on or off according to ANSI T1.403 (LIM0.ARL = 1). The current state of the remote loop is indicated in a status register. Replacing the receive or transmit data with the in-band loop codes is done by LCR1.XLD/XLA. Status and interrupt-status bits inform the user whether loop-up or loop-down code was detected.
Data Sheet
50
2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.4.5
Remote Loop
In the remote loop-back mode, the clock and data recovered from the line inputs RL1/2 or ROID are routed back to the line outputs XL1/2 or XOID via the analog or digital transmitter. As in normal mode, they are also processed by the synchronizer and then sent to the system interface. The remote loop-back mode is selected by setting the control bits LOOP.RL, LOOP.EJATT and LOOP.XJATT. Received data may be looped with or without the transmit jitter attenuator (JATT).
RL1 RL2
Equalizer
Peak Detector
Clock and Data Recovery
JATT
1)
Decoder
RDON RDOP RCLK
Remote Loop
XL1 XL2
Line Driver
Pulse Shaper
JATT
1)
Encoder
XDIN XDIP TCLK
1) JATT either transmit or direction, receive 1) JATT either inin transmitreceive direction
direction or bypassed
ITS10982
Figure 16
Remote Loop Signal Flow
Note: If an external loop shall be switched between RDON/RDOP/RCLK and XDIN/ XDIP/TCLK, the setup/hold time requirements described in the AC characteristics have to be observed. To relax the timing, the edge selection of either the receive or transmit path can be inverted (see register description of LIM4), or an inverter can be placed between RCLK and TCLK externally.
Data Sheet
51
2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.4.6
Local Loop
The local loop-back mode, selected by LOOP.LL = 1, disconnects the receive lines RL12 or ROID from the receiver. It is used in analog input applications (LIM1.ECMIR = 0). Instead of the signals coming from the line, data provided by the system interface is routed through the analog receiver back to the framer interface. The bit stream is transmitted without disturbance on the transmit line. An AIS to the distant end can be enabled by setting LIM1.XAIS without influencing the data looped back to the system interface. The signal codes for transmitter and receiver have to be programmed to be identical.
RL1 RL2
Equalizer
Peak Detector
Clock and Data Recovery
JATT
1)
Decoder
RDON RDOP RCLK
Local Loop
XL1 XL2
Line Driver
Pulse Shaper AIS
JATT
1)
Encoder
XDIN XDIP TCLK
1)
JATT either in transmit or receive direction
ITS10984
Figure 17
Local Loop Signal Flow
Data Sheet
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PEB 22504 QuadLIU V1.1
Interface Description
4.4.7
Digital Loop
The digital loop-back mode, selected by LOOP.DLB = 1, also disconnects the receive lines RL1/2 from the receiver. It is used in digital input applications (LIM1.ECMIR = 1). Instead of the signals coming from the line, the data provided by framer interface is routed through the clock and data recovery circuit back to the framer interface without touching the analog receiver part. The bit stream is transmitted on XL1/2 without disturbance. An AIS to the distant end can be enabled by setting LIM1.XAIS without influencing the data looped back to the framer interface. The serial codes for transmitter and receiver have to be programmed identically.
RL1 RL2
Equalizer
Peak Detector
Clock and Data Recovery
JATT
1)
Decoder
RDON RDOP RCLK
Digital Loop
XL1 XL2
Line Driver
Pulse Shaper AIS
JATT
1)
Encoder
XDIN XDIP TCLK
1)
JATT either in transmit or receive direction
ITS10983
Figure 18
Digital Loop Signal FLow
Data Sheet
53
2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.4.8
Alarm Simulation
Alarm simulation does not affect the normal operation of the device. However, real alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. The alarm simulation is initiated by setting the bit LIM0.SIM. The following alarms are simulated: * * * * * * * Loss of Signal LOS (red alarm) Alarm Indication Signal AIS (blue alarm) Slip indication Code violation counter (AMI, B8ZS, HDB3 Code) increment Pulse-density violation Transmit clock (TCLK) lost PRBS synchronous state indication and PRBS error counter increment
Setting of the bit LIM0.SIM initiates alarm simulation, interrupt status bits are set. Error counting and indication occurs while this bit is set. After it is reset, all simulated error conditions disappear, but the generated interrupt statuses are still pending until the corresponding interrupt status register is read. Alarms such as AIS and LOS are cleared automatically. Interrupt status register and error counters are cleared automatically on read.
Data Sheet
54
2001-02
PEB 22504 QuadLIU V1.1
Interface Description
4.4.9
Transmit Data Performance Monitoring
Alternatively to the receive data performance monitoring (BPV, EXZ, LOS), this function can be switched into the transmit direction to supervise data received on pins XDIP and XDIN (LIM5.XDPM = 1). Transmit data performance monitoring is available only in bypass mode (LIM2.RD(1:0) = 10), and is not available in remote loop configuration. The principle data flow is shown in Figure 19.
LIM2.RD(1:0) XDPM LIM2.RD(1:0) LOS CVC
RDIP RDIN
MUX DPLL MUX DEC
RDOP
MUX
RDON
XDIP XDOP XDON MUX TCLK SYNC CVC DEC ENC LOS Code Violation Counter HDB3/B8ZS decoder HDB3/B8ZS encoder Loss-of-signal detection Line Driver ENC XDIN
TCS
TPE
RDIP/RDIN and XDOP/XDON are internal signals between analog and digital part of the circuit. F0138
Figure 19
Transmit Data Performance Monitoring
Data Sheet
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PEB 22504 QuadLIU V1.1
Operational Description
5
5.1
Operational Description
Operational Overview
The QuadLIUTM can be operated in one of two modes, which is either E1 mode or T1/J1 mode. The device is programmable via a microprocessor interface which enables byte access to all control and status registers. The QuadLIUTM must be initially programmed after reset. General guidelines for initialization are described in "Basic Initialization Settings" on page 57. The status registers are read-only and are updated continuously. Usually the processor reads the status registers periodically to analyze the alarm status. SIgnals (for example RL1/2 receive line) should not be applied before the device is powered up.
5.2
Device Reset
The QuadLIUTM is forced to the reset state if a low signal is input on pin RES (for minimum period, see "Reset" on page 105). During reset, the QuadLIUTM needs an active clock on pin MCLK. All output stages are in a high-impedance state, all internal flip-flops are reset, and most of the control registers are initialized to default values. After reset, the device is initialized to E1 operation.
5.3 5.3.1
Table 11 Register GCR GCR2 LIM0 LIM1 LIM2
Device Initialization Reset Values
Initial Values after Reset Reset Value Meaning 80H 00H 00H 00H 40H FSC is sourced by channel 1, RCLK1 clock source: Channel 1 E1 mode for all four channels, INT function is open drain AMI coding Power up LOS threshold -20 dB, receive threshold 55%
After reset, the QuadLIUTM is initialized with register values listed in Table 11.
Data Sheet
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PEB 22504 QuadLIU V1.1
Operational Description Table 11 Register LIM5 LOOP PCD PCR LCR1 LCR2 LCR3 XPM(2:0) Initial Values after Reset (cont'd) Reset Value Meaning 04H 00H C0H 18H 40H 09H 01H 73H,02H,00H Detailed mode selection Elastic buffer size: 256 bit Local loop off, remote loop off Pulse count "0" for LOS detection is 192 Pulse count "1" for LOS recovery is 24 in 192-bit interval Down code 6 bit, up code 5 bit length In band loop deactivate code is 001 In band loop activate code is 00001 E1 transmit pulse mask for 120 Ohm All interrupts are disabled DCO reference clock: channel 1, RCLK output: DPLL clock, DCO enabled, DCO internal reference clock, Slave mode
IMR0, IMR1 FFH, FF H CMR 08H
5.3.2
Basic Initialization Settings
For a correct start up of the primary access interface, a set of parameters specific to the system and hardware environment must be programmed after RES goes inactive. Both the basic and the operational parameters must be programmed before the activation procedure of the PCM line starts. Such procedures are specified in ITU-T and ETSI recommendations (e.g. fault conditions and consequent actions). Setting optional parameters makes sense mainly when basic operation via the PCM line is guaranteed. Table 12 gives an overview of the most important parameters in terms of signals and control bits that are to be programmed in one of the above steps. The sequence is recommended but not mandatory. Parameters for the basic and operational set up, for example, may be programmed simultaneously.
Data Sheet
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Operational Description Table 12 Basic Set Up Mode select T1/J1 E1 Short-haul Long-haul Master clock frequency select Specification of line interface, clock generation and pulse mask Output driver enable Line interface coding Loss-of-signal detection/recovery conditions Jitter attenuation Initialization Parameters Registers to be Programmed GCR2.PMODx = 1; x = 1 to 4 GCR2.PMODx = 0; x = 1 to 4 LIM1.EQON = 0 LIM1.EQON = 1 GCM(6:1) LIM0 LIM1 XPM(2:0) XPM2.XLT = 0 LIM0.XC(1:0) LIM0.RC(1:0) PCD PCR LOOP.EJATT LOOP.XJATT
Note: Read access to unused register addresses might return random values and therefore must not be done. Undefined bit positions at defined register addresses might return random values and must be masked before the register value is used for further computing. Writing to unused register addresses or reserved registers may produce unpredictable results.
Data Sheet
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Register Description
6
6.1
Table 13 Ch 1
Register Description
Control Register Addresses
Control Register Addresses Register Type Comment GCR GCR2 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 3D 3E 3F 5D 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 LIM0 LIM1 LIM2 LIM3 LIM4 LIM5 CMR LOOP XPM0 XPM1 XPM2 PCD PCR LCR1 LCR2 LCR3 IMR0 IMR1 CMDR GCM1 GCM2 GCM3 GCM4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Global Configuration Register Line Interface Mode 0 Line Interface Mode 1 Line Interface Mode 2 Line Interface Mode 3 Line Interface Mode 4 Line Interface Mode 5 Clock Mode Register Loop Register Transmit Pulse Mask 0 Transmit Pulse Mask 1 Transmit Pulse Mask 2 Pulse Count Detection Pulse Count Recovery Loop Code Register 1 Loop Code Register 2 Loop Code Register 3 Interrupt Mask Register 0 Interrupt Mask Register 1 Command Register Global Clock Mode 1 Global Clock Mode 2 Global Clock Mode 3 Global Clock Mode 4 Page 60 62 64 66 67 68 70 72 74 76 76 76 79 79 80 81 81 82 82 83 84 84 85 85 Ch 3 00 20 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 Ch 4 Global Configuration Register 2 61
Address (hexadecimal) Ch 2
Data Sheet
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Register Description Table 13 Ch 1 Ch 2 Control Register Addresses (cont'd) Register Type Comment GCM5 GCM6 R/W R/W Global Clock Mode 5 Global Clock Mode 6 Page 86 86 Ch 3 5E 5F Ch 4
Address (hexadecimal)
6.2
Detailed Description of Control Registers
Global Configuration Register (Read/Write) Address: 00H Value after reset: 80H 7 GCR GCR.(7:6) SSF(1:0)
0 0 SSF1 SSF0 FSC1 FSC0 R1S1
0
R1S0
reserved, must be cleared Select SYNC Frequency The frequency of the reference clock for the DCO circuitry provided on pin SYNC is selected by these bits. 00 = External SYNC frequency: 2.048 MHz (default) 01 = External SYNC frequency: 1.544 MHz 10 = External SYNC frequency: 8 kHz (master mode only) 11 = Not defined
Data Sheet
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Register Description FSC(1:0) FSC Source One of the four internally generated de-jittered 8-kHz clocks is output on port FSC. 00 = Sourced by channel 1 (default) 01 = Sourced by channel 2 10 = Sourced by channel 3 11 = Sourced by channel 4 R1S(1:0) RCLK1 Source One of the four internally generated receive route clocks is output on port RCLK1 (available for RCLK1 only, not for RCLK(2:4)). 00 = Extracted receive clock of channel 1 (default) 01 = Extracted receive clock of channel 2 10 = Extracted receive clock of channel 3 11 = Extracted receive clock of channel 4 Global Configuration Register 2 (Read/Write) Address: 20H Value after reset: 00H 7 GCR2
0 0 IC1 IC0
0
PMOD4 PMOD3 PMOD2 PMOD1
Note: Unused bits have to be cleared.
GCR2.7 GCR2.6 IC(1:0) reserved reserved Interrupt Pin Control x0 = Open drain, active low (default) 01 = Push-pull, active low 11 = Push-pull, active high PMOD(4:1) E1 or T1/J1 Mode of channel (4:1) 0= 1= E1 mode (default) T1/J1 mode
Data Sheet
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Register Description Line Interface Mode 0 (Read/Write) Addresses: 01H, 21H, 41H, 61H Value after reset: 00H 7 LIM0 XC(1:0)
XC1 XC0 RC1 RC0 EXZE PDE ARL
0
SIM
Transmit Code Serial codes for transmitter and receiver can be programmed independently. The single-rail data stream received on port XDIP is encoded as follows: 00 = AMI 01 = HDB3 code for E1 applications 10 = B8ZS code for T1/J1 applications 11 = Encoder is bypassed, XDIN is used as "data input negative" After any modification of bits XC(1:0), a software reset is required (CMDR.RES = 1). If the encoder is bypassed, hardware tristate function is not available.
RC(1:0)
Receive Code The recovered data is decoded and transmitted on pin RDOP in NonReturn-to-Zero (NRZ) format (single-rail or unipolar data). 00 = AMI 01 = HDB3 code for E1 applications 10 = B8ZS code for T1 applications 11 = Decoder is bypassed; RDON is used as "data output negative" CMI coding is selected by setting LIM1.ECMIR = 1. After any modification of bits RC(1:0), a software reset is required (CMDR.RES = 1).
Data Sheet
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Register Description EXZE Excessive Zeros Detection Enable Selects line code error detection mode. E1 mode (GCR2.PMODx = 0): 0= 1= Only double violations are detected. Extended code violation detection: 0000 strings are detected additionally. Thereafter, incrementation of code violation counter CVC is done after receiving an additional four zeros. Only bipolar violations are detected. Bipolar violations and zero strings of 8 or more contiguous zeros in B8ZS code, or more than 15 contiguous zeros in AMI code, are detected additionally and counted in the CVC.
T1/J1 mode (GCR2.PMODx = 1): 0= 1=
PDE
Pulse-Density Enforcer Selects pulse-density enforcement mode for AMI signals. Pulsedensity according to ANSI T1.403 is enforced automatically. 0= 1= Disabled Enabled
ARL
Automatic Remote Loop 0= 1= Disables automatic on/off switching for the remote loop upon detecting the in-band loop activate/deactivate code. Enables automatic on/off switching for the remote loop upon detecting the in-band loop activate/deactivate code. Activate and deactivate codes are user-programmable. When the inband loop activate code (e.g. 00001) is detected for at least 5 s, the remote loop is automatically switched on until the deactivate code (e.g. 001) is detected for 5 s or the bit LIM0.ARL is cleared. Automatic remote loop switching can be activated with or without jitter attenuation, depending on bit LOOP.EJATT.
SIM
Alarm Simulation 0= 1= Internal alarm simulation inactive. Internal alarm simulation active. Initiates internal error simulation of alarm indication signal, loss-of-signal, slip, code violations, PRBS errors and loss of transmit clock. The CVC and BECL/H error counters are incremented.
Data Sheet
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Register Description Line Interface Mode 1 (Read/Write) Addresses: 02H, 22H, 42H, 62H Value after reset: 00H 7 LIM1 PD
PD EQON ECMIR RDON1 RDON0 ECM ECMIX
0
XAIS
Power Down Switches the appropriate channel between power-up and powerdown mode. 0= 1= Power up Power down
EQON
Receive Equalizer On 0= 1= -10 dB Receiver: short-haul mode -43 dB Receiver: long-haul mode (E1) -36 dB Receiver: long-haul mode (T1/J1)
ECMIR
Enable CMI Receive Interface 0= 1= The ternary interface is selected. Multifunction ports RL1/2 become analog inputs. The digital CMI receive interface is selected. Received data is latched on multifunction port ROID.
RDON(1:0)
RDON Pin Input/Output Multiplexer Select 00 = RDON output 01 = BPV output (bipolar violations) 10 = SCLKO output 11 = SCLKI input
Data Sheet
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Register Description ECM Error Counter Mode The function of the error counters is determined by this bit. 0= Before reading an error counter, the corresponding bit in the command register (CMDR) has to be set. The low byte of the error counter should always be read before the high byte. The error counter is reset with the rising edge of the corresponding bits (DBEC, DCVC) in the CMDR register. Every second the error counter is latched and then reset automatically. The latched error counter state must be read within the next second, otherwise data is overwritten. Avoid reading the error counter during updating.
1=
ECMIX
Enable CMI Transmit Interface 0= 1= The ternary interface is selected. XL1/2 are used as analog outputs. The digital CMI receive interface is selected. Transmitted data is output on port XOID.
XAIS
Transmit AIS towards Remote End 0= 1= Normal transmit operation. Sends AIS via ports XL1/XL2 towards the remote end. The outgoing data stream which can be looped back via the local loop to the framer interface is not affected.
Data Sheet
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Register Description Line Interface Mode 2 (Read/Write) Addresses: 03H, 23H, 43H, 63H Value after reset: 40H 7 LIM2 RIL(2:0)
RIL2 RIL1 RIL0 SLT1 SLT0 0 RD1
0
RD0
Receive Input Threshold Only valid if analog line interface is selected (LIM1.ECMIR = 0 ). "No signal" is declared if the voltage between pins RL1 and RL2 drops below the limit programmed through bits RIL(2:0) and the received data stream has no transition for a period defined in the PCD register. Please see the selectable voltage levels in chapter Chapter 7.3 on page 102.
Note: LIM2.RIL(2:0) must be programmed before LIM1.EQON = 1 is set (long-haul mode).
SLT(1:0) Receive Slicer Threshold 00 = The receive slicer generates a mark (digital one) if the voltage on RL1/2 exceeds 55% of the peak amplitude (default). 01 = The receive slicer generates a mark (digital one) if the voltage on RL1/2 exceeds 67% of the peak amplitude. 10 = The receive slicer generates a mark (digital one) if the voltage on RL1/2 exceeds 50% of the peak amplitude. 11 = The receive slicer generates a mark (digital one) if the voltage on RL1/2 exceeds 45% of the peak amplitude.
Data Sheet
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Register Description RD(1:0) Select Receive Data Output These bits select the different stages of the received data path. 00 = Received data is decoded (HDB3/B8ZS/AMI) and output on RDOP/N. 01 = Data recovered by the DPLL (not decoded) is output on RDOP/N. 10 = Sliced data is transferred directly to RDOP/N. 11 = Sliced data is directly transferred to RDOP/N and the bypassed receive path logic is switched off to reduce power consumption unless remote loop is activated. Line Interface Mode 3 (Read/Write) Addresses: 04H, 24H, 44H, 64H Value after reset: 00H 7 LIM3 LBO(2:1)
LBO2 LBO1 GTP MTP EPRM XPRBS IPRBS
0
SPRBS
Line Build-Out (T1 mode only) In long-haul applications, LIM1.EQON = 1, a transmit filter can be optionally placed in the transmit path to attenuate the signal level on pins XL1/2. Selecting the transmitter attenuation is possible in steps of 7.5 dB at 772kHz, which meets FCC Part 68 and ANSI T1.403. To meet the line build-out characteristics defined by ANSI T1.403, registers XPM(2:0) should be programmed as follows: 00 = 0 dB 01 = -7.5 dB -->XPM(0:2) = 11 H , 02H , 20H 10 = -15 dB -->XPM(0:2) = 8EH , 01H , 20H 11 = -22.5 dB -->XPM(0:2) = 09 H , 01H , 20H
GTP
PRBS/IBL Generator in Transmit Path 0= 1= The PRBS/IBL generator is placed in the receive path. The PRBS/IBL generator is placed in the transmit path.
MTP
PRBS/IBL Monitor in Transmit Path 0= 1= The PRBS/IBL monitor is placed in the receive path. The PRBS/IBL monitor is placed in the transmit path.
Data Sheet
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Register Description EPRM Enable PRBS Monitor 0= 1= XPRBS The PRBS monitor is disabled. The PRBS monitor is enabled.
Transmit Pseudo-Random Bit Sequence (PRBS) 0= 1= Normal transmit operation A "1" in this bit position enables transmission of a pseudorandom bit sequence. Depending on bit SPRBS, the PRBS is generated according to 2 15 -1 or 220-1 (ITU-T O.151).
IPRBS
Invert Pseudo-Random Bit Sequence PRBS 0= 1= The generated PRBS data is not inverted. The PRBS data is inverted. Pseudo-random bit sequence algorithm: 215 -1 Pseudo-random bit sequence algorithm: 220 -1 with maximum 14 consecutive zeros restriction.
SPRBS
Select Pseudo-Random Bit Sequence Algorithm 0= 1=
Line Interface Mode 4 (Read/Write) Addresses: 05H, 25H, 45H, 65H Value after reset: 00H 7 LIM4 RPE
RPE TPE VIS SCI DCF PC2 PC1
0
PC0
RCLK Positive Edge 0= 1= RDOP/N are output with the falling edge of the RCLK clock. RDOP/N are output with the rising edge of the RCLK clock.
TPE
Positive Sample Edge of TCLK 0= 1= XDIP/N are latched with the falling edge of the TCLK clock. XDIP/N are latched with the rising edge of the TCLK clock.
VIS
Masked Interrupts Visible 0= 1= Masked interrupt status bits are not visible in registers ISR(0:1). Masked interrupt status bits are visible in ISR(0:1), but they are not visible in register CIS. Interrupt request pin INT stays inactive.
Data Sheet
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Register Description SCI Status Change Interrupt 0= 1= Interrupts are generated either at the beginning or end of the internal interrupt event. The following interrupts are activated if enabled upon detection and recovering of the internal interrupt source: ISR0.LOS , ISR0.AIS, ISR0.PDENI, ISR1.LTC
DCF
Disable Center Frequency of DCO circuitry Only valid if master mode (CMR.MAS = 1) is selected. 0= 1= Automatic centering of the DCO circuitry is enabled. Automatic centering of the DCO circuitry is disabled.
PC(2:0)
MFP Port Configuration These bits select the output pin function of multifunction port MFP. 000 = Loss-of-signal (red alarm) indication 001 = Analog loss-of-signal indication 010 = Pseudo-random bit sequence synchronization status 011 = Bipolar violation indication 100 = Transmit line short status 101 = Alarm indication signal 110 = Not defined 111 = Not defined
Data Sheet
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Register Description Line Interface Mode 5 (Read/Write) Addresses: 06H, 26H, 46H, 66H Value after reset: 04H 7 LIM5 ACS
ACS XDPM XLB XLM LOSR1
0
LOSR0
Automatic Clock-Switching If TCLK is missing, the transmit clock can optionally be switched to the SYNC clock automatically. 0= 1= Automatic switching is disabled (default); if TCLK is missing, XL1/2 are undefined. Automatic switching is enabled; if TCLK is missing, SYNC is used, if SYNC is also missing, XL1/2 are undefined.
XDPM
Transmit Data Performance Monitoring To verify transmit data, the receive line supervision circuitry can be switched to the transmit path. If selected, data input on pins XDIP/ XDIN is checked for BiPolar Violations (BPV), EXzessive Zeros (EXZ) and Loss Of Signal (LOS). 0= 1= Receive path (default) Transmit path
Note: Transmit data performance monitoring is not possible in remote loop configuration. LIM2.RD(1:0) = 10 is required.
XLB Transmit Line Biasing The analog circuit of the transmit line driver can be switched into a power saving mode. This slightly reduces the output slopes on XL1/2. 0= 1= XLM Normal operation (default) Power-saving operation
Transmit Line Monitor Enable The transmit line monitor circuit can be switched off to reduce power consumption. 0= 1= Transmit line monitor is off. Transmit line monitor is active (default).
Data Sheet
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Register Description LOSR(1:0) Loss-of-Signal Recovery Condition 00 = The LOS alarm is cleared if the predefined pulse-density (register PCR) is detected during the time interval which is defined by register PCD. 01 = In addition to the recovery condition described above a LOS alarm is cleared only if the pulse-density requirement (defined by PCR and PCD) is fulfilled and no more than 15 contiguous zeros are detected during the recovery interval. 10 = A LOS alarm is not terminated, if at the end of the pulse position interval any subinterval of 100 pulse positions contains no pulses of either polarity (ANSI T1.231). This means, clearing a LOS alarm is done only if the pulse-density requirement (defined by PCR and PCD) is fulfilled and no more than 99 contiguous zeros are detected during the recovery interval. 11 = In addition to the recovery condition described for "00" a LOS alarm is cleared only if the pulse-density requirement (defined by PCR and PCD) is fulfilled and no more than 8 contiguous zeros are detected during the recovery interval.
Data Sheet
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Register Description Clock Mode Register (Read/Write). Addresses: 07H, 27H, 47H, 67H Value after reset: 08H , 58H, A8H, F8H 7 CMR DSS(1:0)
DSS1 DSS0 RS1 RS0 DCS SCF ELT
0
MAS
DCO Synchronization Clock Source DCO in receive path: These bits select the reference clock source for the DCO circuitry. 00 = Receive reference clock generated by the DPLL of channel 1 01 = Receive reference clock generated by the DPLL of channel 2 10 = Receive reference clock generated by the DPLL of channel 3 11 = Receive reference clock generated by the DPLL of channel 4 DCO in transmit path: These bits select the reference clock source for the DCO circuitry. 00 = Reference clock for the DCO is TCLK1 01 = Reference clock for the DCO is TCLK2 10 = Reference clock for the DCO is TCLK3 11 = Reference clock for the DCO is TCLK4
Note: After Reset all DCO circuitries synchronize with the clock sourced by the DPLL of channel 1 . Each channel has to be configured individually. If CMR.MAS is set, the DCO circuitry synchronizes with the clock applied on port SYNC.
Data Sheet
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Register Description RS(1:0) Select RCLK Source These bits select the source of RCLK. 00 = Extracted receive clock generated by the DPLL is used If jitter attenuation is selected in receive direction and external SCLKI is not used (LOOP.XJATT = 0, LOOP.EJATT = 1, LIM1.RDON(1:0) 11), de-jittered 2.048 (E1)/1.544 MHz (T1/ J1) clock generated by the internal DCO circuitry is used. 01 = Extracted receive clock; in case of an active LOS alarm RCLK is set high. 10 = De-jittered 2.048 (E1)/1.544 MHz (T1/J1) clock generated by the internal DCO circuitry is used. 11 = Not defined DCS Disable Clock-Switching In slave mode (CMR.MAS = 0), the DCO is synchronized with the recovered route clock. In case of LOS (receive mode) or LSR1.TCS = 1 (transmit mode), the DCO switches to the clock sourced by port SYNC. If this bit is set, automatic switching from RCLK (receive mode) or TCLK (transmit mode) to SYNC is disabled (default). SCF Select Corner Frequency of DCO Setting this bit reduces the corner frequency of the DCO circuit by the factor of ten from 2 Hz (E1)/6 Hz (T1/J1) to 0.2 Hz (E1)/0.6 Hz (T1).
Note: Reduction of the corner frequency of the DCO circuitry increases the time required for synchronization.
ELT Enable Loop-Timed 0= 1= Normal operation Transmit clock is generated from the clock supplied by MCLK, which is synchronized with the extracted receive route clock. In this configuration, the transmit elastic buffer has to be enabled.
MAS
Master Mode 0= 1= Slave mode Master mode on. Setting this bit the DCO circuitry is frequency synchronized with the clock (2.048 MHz, 1.544 MHz or 8 kHz) supplied on pin SYNC. If this pin is connected to V SS or VDD , the DCO circuitry is centered and no receive jitter attenuation is performed. The generated clocks are stable.
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Register Description Loop Register (Read/Write) Addresses: 08H, 28H, 48H, 68H Value after reset: 00H 7 LOOP XJATT
XJATT EJATT RL LL DLB
LOSDAT
0
BS1 BS0
Jitter Attenuator Position 0= 1= The elastic buffer is placed in the receive path. The elastic buffer is placed in the transmit path.
EJATT
Enable Jitter Attenuator 0= 1= The elastic buffer is disabled. The elastic buffer is enabled.
RL
Remote Loop 0= 1= Remote loop is switched off. Remote loop is switched on. The remote loop-back mode disconnects the transmit data received on XDIP/N from the transmitter. Received data on pins RL1/2 is looped back to the line interface with or without jitter attenuation. The decoder and encoder are ignored. If LIM0.ARL (automatic remote loop) is selected and no valid ARL condition is decoded, the remote loop stays active until RL is reset (higher priority of RL compared to ARL)
LL
Local Loop Analog line applications (LIM1.ECMIR = 0) 0= 1= Local loop is switched off. Local loop is switched on. Data received on ports XDIP/N is looped back through the analog receiver to pins RDOP/N. An alarm indication signal (blue signal) can be sent to the remote end (LIM1.XAIS). Data received on ports RL1/2 is ignored. Receiver and transmitter coding must be identical.
DLB
Digital Loop-Back Digital line applications (LIM1.ECMIR = 1) 0= 1= Digital loop-back disabled. Digital loop-back enabled. Data received on ports XDIP/N is looped back to pins RDOP/N. Optinally an alarm indication signal (blue signal) can be sent to the remote end (LIM1.XAIS).
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Register Description Data received on ports RL1/2 is ignored. Receiver and transmitter coding must be identical. LOSDAT Data Stream Clear in Case of LOS 0= 1= BS(1:0) If LOS is detected, data is processed, bit errors may occur If LOS is detected, data is cleared to avoid bit errors
Buffer Size 00 = 256 bits 01 = 128 bits 10 = 64 bits 11 = 32 bits
Data Sheet
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Register Description Transmit Pulse Mask (0:2) (Read/Write) Addresses XPM0: 09H, 29 H, 49 H, 69H Addresses XPM1: 0AH, 2AH, 4AH, 6AH Addresses XPM2: 0BH, 2BH, 4BH, 6BH Value after reset: 73H, 02H, 00H 7 XPM0 XPM1 XPM2
XP12 XP30 XLLP XP11 XP24 XLT XP10 XP23 DAXLT XP04 XP22 XLHC XP03 XP21 XP34 XP02 XP20 XP33 XP01 XP14 XP32
0
XP00 XP13 XP31
The transmit pulse shape is output on pins XL1 and XL2. The level of the pulse shape is programmed via registers XPM(2:0) to create a custom waveform. In order to get an optimized pulse shape for the external transformers, each pulse shape is internally devided into four sub-pulse shapes. In each sub-pulse shape, a programmable 5-bit value defines the level of the analog voltage on pins XL1 and XL2. Together four 5-bit values have to be programmed to form one complete transmit pulse shape. The four 5bit values are sent in the following sequence: XP04 to XP14 to XP24 to XP34 to 00: First pulse shape level 10: Second pulse shape level 20: Third pulse shape level 30: Fourth pulse shape level
Changing the LSB of each subpulse in registers XPM(2:0) changes the amplitude of the differential voltage on XL1/2 by approximately 80 mV.
Data Sheet
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Register Description Example for E1 mode: 120 interface and wired as shown in Figure 13 on page 45. XPM04 to 00: 1BH XPM14 to 10: 1BH XPM24 to 20: 00H XPM34 to 30: 00H Programming values for XPM(0:2): 7BH, 03H, 00 H
Example for T1 mode The XPM values are valid for the following external circuitry: Transformer ratio: 1:2.4; Cable: PULB 22AWG (100 ); Serial resistors: 2 . Table 14 Range in m 0 to 40 40 to 81 81 to 122 Pulse Shaper Programming Range in ft. 0 to 133 XPM0 XPM1 XPM2 XP04XP00 23 24 28 29 31 XP14XP10 22 22 23 23 22 XP24XP20 7 8 10 17 21 XP34XP30 2 2 2 3 3
hexadecimal D7 1E 22 2A C6 D6 11 11 11 11 11 133 to 266 D8 266 to 399 FC
decimal
122 to 162 399 to 533 FD 162 to 200 533 to 655 DF
Data Sheet
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Register Description XLLP Reserved 0= 1= XLT Normal operation Reserved (not to be used)
Transmit Line Tristate 0= 1= Normal operation Transmit line XL1/XL2 is switched into high-impedance state. If this bit is set, the transmit line monitor status information is frozen. This bit is functionally ored with pin TRIST unless XDIN function is used during decoder bypass.
DAXLT
Disable Automatic Tristating of XL1/2 0= Normal operation. If a short is detected on pins XL1/2, the transmit line monitor sets the XL1/2 outputs into a highimpedance state. If a short is detected on XL1/2 pins, automatically setting these pins into a high-impedance (by the XL-monitor) state is disabled.
1=
XLHC
Transmit Line High Current 0= 1= Output current less than 50 mA Output current more than 50 mA To be selected for T1/J1 mode or E1 mode.
Data Sheet
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Register Description Pulse Count Detection Register (Read/Write) Addresses: 0CH, 2C H, 4CH, 6CH Value after reset: C0H 7 PCD PCD(7:0)
PCD7
0
PCD0
Pulse Count Detection An LOS alarm is detected if the incoming data stream has no transitions for a programmable number T of consecutive pulse positions. The number T is programmable via the PCD register and can be calculated as follows: T = 16 x (PCD+1) ; with 0 PCD 255. The maximum time is 256 x 16 x 488 ns = 2 ms in E1 mode, or 256 x 16 x 648 ns = 2.65 ms in T1 mode. Every detected pulse resets the internal pulse counter. The counter is clocked with the receive clock RCLK.
Pulse Count Recovery (Read/Write) Addresses: 0DH, 2D H, 4DH, 6DH Value after reset: 18H 7 PCR PCR(7:0)
PCR7
0
PCR0
Pulse Count Recovery An LOS alarm is cleared if a pulse-density is detected in the received bit stream. The number of pulses M which must occur in the predefined PCD time interval is programmable via the PCR register, and can be calculated as follows: M = N + 1 ; with 0 N 255. The time interval starts with the first detected pulse transition. With every received pulse, a counter is incremented and the actual counter is compared with the contents of PCR register. If the pulse number is greater or equal to the PCR value, the LOS alarm is reset. Otherwise the alarm stays active. In this case, the next detected pulse transition starts a new time interval.
Data Sheet
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Register Description Loop Code Register 1 (Read/Write)1) Addresses: 0EH, 2EH, 4E H, 6EH Value after reset: 40H 7 LCR1
LDCL1 LDCL0 LACL1 LACL0 XLD
0
XLA
LDCL(1:0)
Length Deactivate (Down) Code These bits defines the length of the user-programmable LLB deactivate code, which is programmable in register LCR2. 00 = 5 bit 01 = 6 bit (default) 10 = 7 bit 11 = 8 bit If a shorter pattern length is required, select a multiple of the required length and repeat the pattern in LCR2.
LACL(1:0)
Length Activate (Up) Code These bits defines the length of the user-programmable LLB activate code, which is programmable in register LCR3. 00 = 5 bit (default) 01 = 6 bit 10 = 7 bit 11 = 8 bit If a shorter pattern length is required, select a multiple of the required length and repeat the pattern in LCR3.
XLD
Transmit LLB Deactivate (Down) Code 0= 1= Normal operation (default) Normal data is replaced by the LLB deactivation code continuously until this bit is reset. LCR1.XLA and LIM3.XPRBS must be cleared. LLB deactivate code can be inserted in receive (LIM3.GTP = 0) or transmit direction (LIM3.GTP = 1).
1)
Terms "Line Loop Back" (LLB) and "In Band Loop" (IBL) are synonyms.
Data Sheet
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PEB 22504 QuadLIU V1.1
Register Description XLA Transmit LLB Activate (Up) Code 0= 1= Normal operation (default) Normal data is replaced by the LLB activate code continuously until this bit is reset. LCR1.XLD and LIM3.XPRBS must be cleared. LLB activate code can be inserted in receive (LIM3.GTP = 0) or transmit direction (LIM3.GTP = 1).
Loop Code Register 2 (Read/Write) Addresses: 0FH, 2FH, 4F H, 6F H Value after reset: 09H 7 LCR2 LDC(7:0)
LDC7
0
LDC0
Line Loop-Back Deactivate Code If enabled by bit LCR1.XLD, the LLB deactivate code is repeated automatically until the LLB generator is stopped. Transmit data is overwritten by the LLB code. LDC0 is transmittted last. If the selected code length is less than 8 bits, the leftmost bits of LCR2 are ignored. For correct operations, bit LIM3.XPRBS has to be cleared. The default setting is (00)001001 (6-bit mode is default in LCR1). This generates the standard deactivation code "001".
Loop Code Register 3 (Read/Write) Addresses: 10H, 30H, 50H, 70H Value after reset: 01H 7 LCR3 LAC(7:0)
LAC7
0
LAC0
Line Loop-Back Activate Code If enabled by bit LCR1.XLA, the LLB activate code is repeated automatically until the LLB generator is stopped. Transmit data is overwritten by the LLB code. LAC0 is transmittted last. If the selected code length is less than 8 bits, the leftmost bits of LCR3 are ignored. For correct operations, bit LIM3.XPRBS has to be cleared. The
Data Sheet
81
2001-02
PEB 22504 QuadLIU V1.1
Register Description default setting is (000)00001 (5-bit mode is default in LCR1). This generates the standard activate code "00001". Example: Transmit LLB/IBL activate Code = 00001 Register setting LCR1: xx00xx01 Register setting LCR3: xxx00001
Interrupt Mask Register (0:1) (Read/Write) Addresses IMR0: 11H, 31H, 51H, 71H Addresses IMR1: 12H, 32H, 52H, 72H Value after reset: FFH, FFH 7 IMR0 IMR1 IMR(0:1) Interrupt Mask Register Each interrupt source can generate an interrupt signal on port INT. A "1" in a bit position of IMR(0:1) sets the mask active for the interrupt status in ISR(0:1). Masked interrupt statuses neither generate a signal on INT, nor are they visible in register CIS. Moreover, they are - not displayed in the ISR if bit LIM4.VIS is cleared - displayed in the ISR if bit LIM4.VIS is set
LLBSCM XLSCM PRBSSCM SLNM SLPM PDENM AISM LTCM
0
LOSM SECM
Note: After reset, all interrupts are disabled. See register ISR0/1 for detailed description of bit functions.
Data Sheet
82
2001-02
PEB 22504 QuadLIU V1.1
Register Description Command Register (Read/Write) Addresses: 13H, 33H, 53H, 73H Value after reset: 00H 7 CMDR
RES IBV IPE CEB DBEC
0
DCVC
Note: The maximum time between writing to the CMDR register and the execution of the command takes 2.5 periods of the current line data rate. Register bits are set by software and reset by hardware automatically after the required operation has been completed. Register bits in CMDR cannot be reset by software.
RES Reset Receiver and Transmitter The receive and the transmit line interface (except the clock and data recovery unit DPLL) are reset. The contents of the control registers is not deleted. IBV Insert Bipolar Violations Setting this bit forces a bipolar violation in the transmit data stream. Violations are inserted at the next possible position. Ones preceded by two or more zeros are not converted into violations. Example (V = inserted violation): 001000010100 is converted to 001000010V00 IPE Insert PRBS Error Setting this bit forces a PRBS error in the outgoing data stream (if PRBS transmission is enabled). CEB Center Elastic Buffer Setting this bit forces the delay through the elastic buffer to half of the current buffer size (LOOP.BS1/0). DBEC Disable Pseudo-Random Binary Sequence Error Counter This bit is only valid if LIM1.ECM is cleared. It must be set before reading the error counter. This bit is reset automatically if the corresponding error counter high byte has been read. With the rising edge of this bit the error counter is latched and then cleared. DCVC Disable Code Violation Counter See bit DBEC.
Data Sheet 83 2001-02
PEB 22504 QuadLIU V1.1
Register Description Global Clock Mode Register 1 (Read/Write) Address: 3DH Value after reset: 00H 7 GCM1 0
PHD_E17 PHD_E16 PHD_E15 PHD_E14 PHD_E13 PHD_E12 PHD_E11 PHD_E10
PHD_E1(0:7)
Frequency Adjust for E1 For details, see "Flexible Clock Mode Settings" on page 87.
Global Clock Mode Register 2 (Read/Write) Address: 3EH Value after reset: 00H 7 GCM2 0
DVM_E12 DVM_E11 DVM_E10 VFREQ_EN PHD_E111 PHD_E110 PHD_E19 PHD_E18
DVM_E1(0:2)
Divider Mode for E1 000 = Not valid 001 = DIV_E1 = 3 010 = DIV_E1 = 4 1/6 011 = DIV_E1 = 4 100 = DIV_E1 = 5.5 101 = DIV_E1 = 5 1/3 110 = DIV_E1 = 5 2/3 111 = Not valid
VFREQ_EN
Variable Frequency Enable 0= 1= Fixed clock frequency of 2.048 (E1) or 1.544 MHz (T1/J1) Variable master clock frequency
PHD_E1(8:11)
Frequency Adjust for E1 For details, see "Flexible Clock Mode Settings" on page 87.
Data Sheet
84
2001-02
PEB 22504 QuadLIU V1.1
Register Description Global Clock Mode Register 3 (Read/Write) Address: 3FH Value after reset: 00H 7 GCM3
PHD_T1 7 PHD_T1 6 PHD_T1 5 PHD_T1 4 PHD_T1 3 PHD_T1 2 PHD_T1 1
0
PHD_T1 0
PHD_T1(0:7)
Frequency Adjust for T1 For details, see "Flexible Clock Mode Settings" on page 87.
Global Clock Mode Register 4 (Read/Write) Address: 5DH Value after reset: 00H 7 GCM4
DVM_T12 DVM_T11 DVM_T10 0 PHD_T1 11 PHD_T1 10 PHD_T1 9
0
PHD_T1 8
DVM_T1(0:2)
Divider Mode for T1 000 = Not valid 001 = DIV_T1 = 3 010 = DIV_T1 = 4 1/6 011 = DIV_T1 = 4 100 = DIV_T1 = 5.5 101 = DIV_T1 = 5 1/3 110 = DIV_T1 = 5 2/3 111 = Not valid
PHD_T1(8:11)
Frequency Adjust for T1 For details, see "Flexible Clock Mode Settings" on page 87.
Data Sheet
85
2001-02
PEB 22504 QuadLIU V1.1
Register Description Global Clock Mode Register 5 (Read/Write) Address: 5EH Value after reset: 00H 7 GCM5
MCLK_ LOW PLL_M 4 PLL_M 3 PLL_M 2 PLL_M 1
0
PLL_M 0
MCLK_LOW
Master Clock Range Low 0= 1= Master clock frequency divided by (PLL_M + 1) is greater than or equal to 1.5 MHz Master clock frequency divided by (PLL_M + 1) is less than 1.5 MHz
PLL_M(0:4)
PLL Dividing Factor M For details, see "Flexible Clock Mode Settings" on page 87.
Note: Write operations to GCM5 initiate a PLL reset (see below).
Global Clock Mode Register 6 (Read/Write) Address: 5FH Value after reset: 00H 7 GCM6
PLL_N 4 PLL_N 3 PLL_N 2 PLL_N 1
0
PLL_N 0
PLL_N(0:4)
PLL Dividing Factor N For details, see "Flexible Clock Mode Settings" on page 87.
Note: Write operations to GCM6 initiate a PLL reset (see below).
Data Sheet
86
2001-02
PEB 22504 QuadLIU V1.1
Register Description Flexible Clock Mode Settings If flexible master clock mode is used (VFREQ_EN = 1), the according register settings can be calculated as follows (a windows-based program for automatic calculation is available, see Chapter 9.2 on page 119). For some of the standard frequencies see the table below. 1. PLL_M and PLL_N must satisfy the equations: a. 1.5 MHz fMCLK/(PLL_M + 1) 2.048 MHz b. If a. is not possible, set MCLK_LOW and fulfill 1.02 MHz fMCLK/(PLL_M + 1) 1.5 MHz c. 65 MHz fMCLK x (2xPLL_N + 2)/(PLL_M + 1) 69.7 MHz (as high as possible within this range) 2. Selection of best dividing mode: foutE1 = ( fMCLK x (2xPLL_N+2)/(PLL_M+1) )/DIV_E1 (target E1: 16.384 MHz) foutT1 = ( fMCLK x (2xPLL_N+2)/(PLL_M+1) )/DIV_T1 (target T1: 12.352 MHz) If the target frequency cannot be reached exactly, the dividing mode has to be selected to reach a frequency that is as near as possible to the target frequency. 3. Calculation of correction value (frequency mismatch correction) PHD_E1 = 6 x 4096 x [DIV_E1 - (2xPLL_N+2)/(PLL_M+1) x (fMCLK/16.384 MHz)] PHD_T1 = 6 x 4096 x [DIV_T1 - (2xPLL_N+2)/(PLL_M+1) x (fMCLK/12.352 MHz)] The result of these equations is between -2048 and +2047. Negative values are represented in 2s-complement format (e.g., -2000D = 830 H; +2000D = 7D0H). Table 15 fMCLK [MHz] 1.544 2.048 8.192 10.000 12.352 Clock Mode Register Settings for E1 or T1/J1 GCM1 F0H 00H 00H 90H F0H GCM2 51H 58H 58H 51H 51H GCM3 00H D2H D2H 81H 00H
87
GCM4 80H C2H C2H 8FH 80H
GCM5 00H 00H 03H 04H 07H
GCM6 15H 10H 10H 10H 15H
2001-02
Data Sheet
PEB 22504 QuadLIU V1.1
Register Description
6.3
Table 16 Ch 1 14 15 16 17 18 19 1A 1B 1C
Status Register Addresses
Status Register Addresses Register Type Comment LSR0 LSR1 RES ISR0 ISR1 CVCL CVCH BECL BECH CIS VSTR R R R R R R R R R R R Line Status Register 0 Line Status Register 1 Receive Equalizer Status Interrupt Status Register 0 Interrupt Status Register 1 Code Violation Counter Low Code Violation Counter High PRBS Bit Error Counter Low PRBS Bit Error Counter High Channel Interrupt Status Version Status Register
1)
Address (hexadecimal) Ch 2 34 35 36 37 38 39 3A 3B 3C 60 7F
1)
Page 89 91 92 93 94 96 96 97 97 95 97
Ch 3 54 55 56 57 58 59 5A 5B 5C
Ch 4 74 75 76 77 78 79 7A 7B 7C
The device version number for PEB 22504 V1.1 is 00h.
Data Sheet
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PEB 22504 QuadLIU V1.1
Register Description
6.4
Detailed Description of Status Registers
Line Status Register 0 (Read) Addresses: 14H, 34H, 54H, 74H 7 LSR0 LOS
LOS AIS PDEN EXZD RLS PRBSS LLBAD
0
LLBDD
Loss-of-Signal (Red Alarm) The loss-of-signal (LOS) detection offers the flexibility to fulfill allmost all LOS requirements on the market (e.g. ANSI T1.403/231, TR-WT-499, ITU-T G.775, ETS 300233). Detection: This bit is set when the incoming signal has no transitions in a time interval of T consecutive pulses, where T is programmable via PCD register. Total count of consecutive pulses: 16 < T < 4096. The receive signal level where "no transition" is declared is defined by the programmed value of LIM2.RIL(2:0). Recovery: The bit is reset when the incoming signal has transitions with signal levels greater than the programmed receive input level (LIM2.RIL(2:0)) for at least M pulse periods defined by register PCR in the PCD time interval. An interrupt status bit (ISR0.LOS) is set with the rising edge of this bit. For additional recovery conditions according to ANSI T1.231, refer also to register LIM5.LOSR(1:0). The bit is also set during alarm simulation, and is reset if LIM0.SIM is cleared and no alarm condition exists.
AIS
Alarm Indication Signal (Blue Alarm) The AIS alarm is detected according to ITU-T G.775 and ANSI T1.231 standards. E1 mode: This bit is set when the incoming signal has fewer than three zeros in each of two consecutive 512-bit periods. This bit is cleared when each of two consecutive 512-bit periods contains three or more zeros.
Data Sheet
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PEB 22504 QuadLIU V1.1
Register Description T1/J1 mode: This bit is set when fewer than six zeros are detected within a time interval of 3 ms received on RL1/2. The bit is also set during alarm simulation, and reset if LIM0.SIM is cleared and no alarm condition exists. An interrupt status bit (ISR0.AIS) is set with the rising edge of this bit. PDEN Pulse-Density Violation This bit indicates that the pulse-density of the received data stream defined by ANSI T1.403 is violated. More than 15 consectuive zeros or fewer than N ones are detected in each time window of 8 x (N+1) digit time slots with N taking on all values of 1 to 23. The bit is cleared if the pulse-density fulfills the above requirement within 23 received ones or automatically after a read access. The bit is also set during alarm simulation. EXZD Exzessive Zeros Detected Significant only if exzessive zero detection is enabled by setting LIM0.EXZE = 1. Detection is done according to ANSI T1.231 requirements. The bit is set after detection of more than three (HDB3;E1), seven (B8ZS ;T1/J1) or 15 (AMI;T1/J1) contiguous zeros in the received bit stream. This bit is cleared when read. RLS Remote Loop Status Any change of this bit causes an ISR0.LLBSC interrupt. 0= The remote loop is inactive. If enabled by bit LIM0.ARL, the remote loop is switched off automatically upon detection of the in-band loop deactivate code for at least 5 s, according to ANSI T1. 403 requirements. The remote loop is active (closed). If enabled by bit LIM0.ARL, the remote loop is switched on automatically upon detection of the in-band loop activate code for at least 5 s.
1=
PRBSS
Pseudo-Random Binary Sequence Status The current status of the PRBS synchronizer is indicated in this bit. It is set if the synchronous state is reached, even in the presence of a bit error rate less than or equal to 10-1. A data stream containing all zeros with or without framing bits is also a valid pseudo-random bit sequence. The bit is also set during alarm simulation.
Data Sheet
90
2001-02
PEB 22504 QuadLIU V1.1
Register Description LLBDD Line Loop-Back Deactivation Signal Detected This bit is set if the LLB deactivate signal is detected and then received over a period of more than 25 ms (E1) or 33.16 ms (T1) ,with a bit error rate less than 10-2. The bit remains set as long as the bit error rate does not exceed 10-2. If automatic remote loop switching is disabled (LIM0.ARL = 0), any change of this bit causes an LLBSC interrupt. LLBAD Line Loop-Back Activation Signal Detected This bit is set if the LLB activate signal is detected and then received over a period of more than 25 ms (E1) or 33.16 ms (T1), with a bit error rate less than 10-2. The bit remains set as long as the bit error rate does not exceed 10 -2. If automatic remote loop switching is disabled (LIM0.ARL = 0), any change of this bit causes an LLBSC interrupt. Line Status Register 1 (Read) Addresses: 15H, 35H, 55H, 75H 7 LSR1 TCS Transmit Clock Status This bit is set if the transmit clock derived from TCLK failed to occur for at least eight TCLK periods. The DCO reference is switched to SYNC if not disabled by CMR.DCS. The transmit lines XL1/2 are tristated automatically. With the first detected edge of the transmit clock, this bit is cleared and tristating of XL1/2 is disabled. Additionally, the interrupt status bit ISR1.LTC is set. MCLK must be active because the reference frequency to detect a TCLK loss is derived from this clock. The bit is also set during alarm simulation. XLS Transmit Line Short Significant only if the ternary line interface is selected by LIM1.ECMIX = 0. 0= Normal operation. No short is detected.
TCS XLS
0
XLO
1 = The XL1 and XL2 are shortened for at least three pulses. As a reaction of the short, pins XL1 and XL2 are automatically forced into a high-impedance state if bit XPM2.DAXLT is reset. After 128 consecutive pulse periods, outputs XL1/2 are activated again and the
Data Sheet 91 2001-02
PEB 22504 QuadLIU V1.1
Register Description internal transmit current limiter is checked. If a short between XL1/2 is still active, outputs XL1/2 are in high-impedance state again. When the short disappears, pins XL1/2 are activated automatically and this bit is reset. With any change of this bit, an interrupt ISR0.XLSC is generated. If XPM2.XLT is set, this bit is frozen. XLO Transmit Line Open 0= 1= Normal operation This bit is set if at least 32 consecutive zeros were sent via pins XL1/XL2. This bit is reset with the first transmitted pulse. An interrupt ISR0.XLSC is set with the rising edge of this bit. If XPM2.XLT is set, this bit is frozen.
Receive Equalizer Status (Read) Addresses: 16H, 36H, 56H, 76H 7 RES EV(1:0)
EV1 EV0 RES4 RES3 RES2 RES1
0
RES0
Equalizer Status Valid These bits inform the user about the current state of the receive equalization network. Only valid if LIM1.EQON is set. 00 = Equalizer status not valid, still adapting 01 = Equalizer status valid 10 = Equalizer status not valid 11 = Equalizer status valid but high noise floor
RES(4:0)
Receive Equalizer Status These bits display current line attenuation status in steps of approximately 1.4 (T1J1)1.7 (E1) dB. Only valid if bits EV(1:0) = 01. Accuracy: 2 digits, based on temperature influence and noise amplitude variations. 00000 = Minimum gain (0 dB) ... 11001 = Maximum equalizer gain
Note: For maximum receiver sensitivity set bits LIM2.RIL(2:0) = 110
Data Sheet
92
2001-02
PEB 22504 QuadLIU V1.1
Register Description Interrupt Status Register 0 (Read) Addresses: 17H, 37H, 57H, 77H Value after reset: 00H 7 ISR0
LLBSC XLSC PRBSSC SLN SLP PDENI AIS
0
LOS
All bits are reset when ISR0 is read. If bit LIM4.VIS is set, interrupt statuses in ISR0 may be flagged although they are masked via register IMR0. However, these masked interrupt statuses neither generate a signal on INT, nor are they visible in register CIS. LLBSC Line Loop Back Status Change Depending on bit LIM0.ARL the interrupt source is changed. LIM0.ARL = 0 : This bit is set if the LLB activate signal or the LLB deactivate signal is detected over a period of 25 ms/33.16 ms (E1/T1) with a bit error rate less than 10-2. The LLBSC bit is also set if the current detection status is left, i.e., if the bit error rate exceeds 10-2. LIM0.ARL = 1 : This bit is set high with any change of state of bit LSR0.RLS. XLSC Transmit Line Status Change XLSC is set with the rising edge of the bit LSR1.XLO or with any change of bit LSR1.XLS. The actual status of the transmit line monitor can be read from LSR1.XLS and LSR1.XLO. PRBSSC PRBS Status Change This bit is set with any change of state of the PRBS synchronizer. The current status of the PRBS synchronizer is indicated in LSR0.PRBSS. SLN Slip Negative The frequency of the receive route clock is greater than the frequency of the receive framer interface working clock based on 2.048 MHz (E1)/1.544 MHz (T1/J1). Data is skipped. SLN is also set during alarm simulation.
Data Sheet
93
2001-02
PEB 22504 QuadLIU V1.1
Register Description SLP Slip Positive The frequency of the receive route clock is less than the frequency of the receive framer interface working clock, which is a multiple of or equal to 2.048 MHz (E1)1.544 MHz (T1/J1). Data is repeated. SLP is also set during alarm simulation. PDENI Pulse-Density Violation Interrupt This bit is set if a pulse-density violation is detected(LSR0.PDEN = 1). The bit is set during alarm simulation. AIS Alarm Indication Signal (Blue Alarm) This bit is set when an alarm indication signal is detected and bit LSR0.AIS is set. It is also set during alarm simulation. If LIM4.SCI is set, this interrupt status bit is set with every change of LSR0.AIS. LOS Loss-of-Signal (Red Alarm) This bit is set when a loss-of-signal alarm is detected in the received bit stream and LSR0.LOS is set. It is also set during alarm simulation. If LIM4.SCI is set, this interrupt status bit is set with every change of LSR0.LOS. Interrupt Status Register 1 (Read) Addresses: 18H, 38H, 58H, 78H 7 ISR1 All bits are reset when ISR1 is read. If bit LIM4.VIS is set, interrupt statuses in ISR1 may be flagged although they are masked via register IMR1. However, these masked interrupt statuses neither generate a signal on INT, nor are they visible in register CIS. LTC Loss of Transmit Clock This bit is set when a loss of transmit clock is detected and bit LSR1.TCS is set. It is also set during alarm simulation. If LIM4.SCI is set, this interrupt status bit is set with every change of LSR1.TCS.
LTC
0
SEC
Data Sheet
94
2001-02
PEB 22504 QuadLIU V1.1
Register Description SEC One-Second Timer The internal one-second timer has expired. The timer is derived from clock RCLK, SCLKO, SCLKI or TCLK, depending on the monitor block configuration. The selected clock source has to supply a constant clock to ensure the correct function of the second timer. Channel Interrupt Status Register (Read) Address: 60H Value after reset: 00H 7 CIS
GIS4 GIS3 GIS2
0
GIS1
This status register points to pending interrupts sourced by ISR1 and ISR0 of each channel. GIS4 GIS3 GIS2 GIS1 Global interrupt status of register ISR1/0 of channel 4 Global interrupt status of register ISR1/0 of channel 3 Global interrupt status of register ISR1/0 of channel 2 Global interrupt status of register ISR1/0 of channel 1
Data Sheet
95
2001-02
PEB 22504 QuadLIU V1.1
Register Description Code Violation Counter (Read) Addresses CVCL: 19H, 39 H, 59 H, 79 H Addresses CVCH: 1AH, 3AH, 5AH, 7AH 7 CVCL
CV7
0
CV0
7 CVCH CV(15:0)
CV15
0
CV8
Code Violations E1 mode: If the HDB3 or the CMI code is selected, the 16-bit counter is incremented if violations of the HDB3 code are detected. The error detection mode is determined by programming the bit LIM0.EXZE. If simple AMI coding is enabled (LIM0.RC(1:0) = 00), all bipolar violations are counted. T1 mode: If the B8ZS code (bit LIM0.RC(1:0) = 10, GCR2.PMODx = 1) is selected, the 16-bit counter is incremented upon detection of violations that are not due to zero substitution. If LIM0.EXZE is set, excessive zero strings (more than seven contiguous zeros) are detected and counted. If simple AMI coding is enabled (LIM0.RC(1:0) = 00), all bipolar violations are counted. If LIM0.EXZE is set, excessive zero strings (more than 15 contiguous zeros) are detected and counted. During alarm simulation, the counter is incremented every four bits received up to its saturation. Clearing and updating the counter is done according to bit LIM1.ECM. If this bit is cleared, the error counter buffer is permanently updated. For correct read access of the error counter, bit CMDR.DCVC has to be set. With the rising edge of this bit, updating of the buffer is stopped and the error counter is cleared. Bit CMDR.DCVC is reset automatically with a read access to the error counter high byte. If LIM1.ECM is set every second (interrupt ISR1.SEC), the error counter is latched and then reset automatically. The latched error counter state has to be read within the next second.
Data Sheet
96
2001-02
PEB 22504 QuadLIU V1.1
Register Description PRBS Bit Error Counter (Read) Addresses CVCL: 1BH, 3B H, 5BH, 7BH Addresses CVCH: 1CH, 3CH, 5CH, 7C H 7 BECL
BEC7
0
BEC0
7 BECH
BEC15
0
BEC8
BEC(15:0)
PRBS Bit Error Counter This 16-bit counter is incremented with every received PRBS bit error in the PRBS synchronous state LSR0.PRBSS = 1. Clearing and updating of the counter is done according to bit LIM1.ECM. If this bit is cleared, the error counter buffer is permanently updated. For correct read access of the error counter bit CMDR.DBEC has to be set. With the rising edge of this bit, updating the buffer is stopped and the error counter is cleared. Bit CMDR.DBEC is reset automatically with a read access to the error counter high byte. If LIM1.ECM is set every second (interrupt ISR1.SEC) the error counter is latched and then cleared automatically. The latched error counter state has to be read within the next second.
Version Status Register (Read) Address: 7FH 7 VSTR VN(7:0)
VN7 VN6
VN5 VN4 VN3 VN2 VN1
0
VN0
Version Number of the Chip 00H =Version 1.1
Data Sheet
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PEB 22504 QuadLIU V1.1
Electrical Characteristics
7
7.1
Table 17 Parameter
Electrical Characteristics
Absolute Maximum Ratings
Maximum Ratings Symbol Limit Values - 40 to 85 - 65 to 150 - 0.4 to 6.5 - 0.4 to 6.5 - 0.4 to 6.5 - 0.4 to 6.5 Unit C C V V V V V
Ambient temperature under bias Storage temperature IC supply voltage (digital) IC supply voltage receive (analog) IC supply voltage transmit (analog) Voltage on any pin with respect to ground ESD robustness HBM: 1.5 k, 100 pF
1)
TA Tstg VDD VDDR VDDX VS
1)
VESD,HBM 2000
According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.
Note: Stresses greater than those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may reduce device reliability.
Data Sheet
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PEB 22504 QuadLIU V1.1
Electrical Characteristics
7.2
Table 18 Parameter
Operating Range
Power Supply Range Symbol Limit Values min. max. 85 3.46 C V
1)
Unit Test Condition
Ambient temperature Supply voltages
Digital input voltages Ground
TA VDD VDDR VDDX VID VSS VSSR VSSX
-40 3.13
0 0
5.25 0
V V
1)
Voltage ripple on analog supply less than 50 mV
Note: In the operating range, the functions given in the circuit description are fulfilled. VDD , VDDR and VDDX have to be connected to the same voltage level, VSS, VSSR and VSSX have to be connected to ground level.
Data Sheet
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PEB 22504 QuadLIU V1.1
Electrical Characteristics
7.3
Table 19 Parameter
DC Characteristics
DC Parameters Symbol Limit Values min. max. 0.8 5.25 0.45 2.4 165 200 35 V V V V mA mA mA
1) 1)
Unit Notes
Input low voltage Input high voltage Output low voltage Output high voltage Average power supply current (Analog line interface) Average power supply current (Digital line interface) Input leakage current Input leakage current Input leakage current Input leakage current Input pullup current
VILSW VIHSW VOL VOH IDDE1 IDDT1 IDD
- 0.4 2.0
IOL = + 2 mA 1) IOH = - 2 mA 1)
E1 application2) T1/J1 application3)
IIL11 IIL12 IIL21 IIL22 IIPU
2
1 1 2.5 2.5 25
A A A A A
VIN = VDD4) VIN = VSS 4 VIN = VDD; only
XL1, XL2
VIN = VSS ; only
XL1, XL2
VIN = VSS; VDD = 5.0V
(typ.: 12 A)
2
25
A
VIN =VSS; VDD = 3.3V
(typ.: 12 A)
Output leakage current
IOZ
1
A
VOUT = tristate1) VSS < Vmeas < VDD
measures against VDD and VSS
Transmitter output impedance
RX
3 105 2.5
mA V
applies to XL1and XL25) XL1, XL2
Transmitter output current IX Transmitter output voltage VX
VDD = 3.3V 6)
Data Sheet
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PEB 22504 QuadLIU V1.1
Electrical Characteristics Table 19 DC Parameters (cont'd) Symbol Limit Values min. Differential peak voltage of VDX a mark (between XL1 and XL2) Receiver differential peak voltage of a mark (between RL1 and RL2) max. 2.15 V XL1, XL2 Unit Notes
Parameter (cont'd)
VDD = 3.3V
VDDR + 0.3 50 (typical value) 0 -10 V RL1, RL2
VR
Receiver input impedance ZR Receiver sensitivity
k dB
5)
SRSH
RL1, RL2 LIM0.EQON = 0 (short-haul) RL1, RL2 LIM0.EQON = 1 (T1/J1, long-haul) RL1, RL2 LIM0.EQON = 1 (E1, long-haul)
Receiver sensitivity
SRLH
0
-36
dB
-36
Receiver input threshold
VRTH
45 50 55 67 (typical value) %
LIM2.SLT(1:0) = 11 = 10 = 00 = 01
5)
Data Sheet
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Electrical Characteristics Table 19 DC Parameters (cont'd) Symbol Limit Values min. Loss-Of-Signal (LOS) detection limit in shorthaul mode max. V RIL(2:0) RIL(2:0) RIL(2:0) RIL(2:0) RIL(2:0) RIL(2:0) RIL(2:0) RIL(2:0)
5) 7)
Parameter (cont'd)
Unit Notes = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111
VLOSSH
0.90 0.70 0.60 0.40 0.30 0.20 0.15 0.10 (typical values) 1.70 0.85 0.85 0.45 0.45 0.20 0.10 not defined (typical values)
LOS detection limit in long-haul mode
VLOSLH
V
RIL(2:0) RIL(2:0) RIL(2:0) RIL(2:0) RIL(2:0) RIL(2:0) RIL(2:0) RIL(2:0)
5) 7)
= 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111
1) 2)
Applies to all pins except analog pins RLx, TLx Wiring conditions and external circuit configuration according to Figure 13 on page 45 for E1 mode 120 ; PRBS signal; four channels active; values of registers XPM(2:0) = 00H, 03H, 7BH Wiring conditions and external circuit configuration according to Figure 13 on page 45 for T1 mode; PRBS signal; four channels active; values of registers XPM(2:0) = 11H, 1EH, D7H Applies to all pins except RCLK, SCLKR, RL1, RL2, XL1, XL2 Parameter not tested in production Depending on external configuration Differential input voltage between pins RL1 and RL2; depends on programming of register LIM2.RIL(2:0)
3)
4) 5) 6) 7)
Note: Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and 3.3V supply voltage.
Data Sheet
102
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
7.4 7.4.1
AC Characteristics Master Clock Timing
1 2 3
MCLK
F0007
Figure 20 Table 20 No. 1
MCLK Timing MCLK Timing Parameter Values Limit Values min. typ. 488 648 50 max. ns ns 980.4 ns % % 28 ppm
1) 2)
Parameter Clock period of MCLK
Unit
Condition E1, fixed mode T1/J1, fixed mode flexible mode
2 3
1) 2)
High phase of MCLK Low phase of MCLK Clock accuracy
to reach an internal clock accuracy of 32 ppm
40 40 32
depends on master clock frequency selection / rounding of clock divider setting
Data Sheet
103
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
7.4.2
JTAG Boundary Scan Interface
80 81 82
TCK 83 84 TMS 85 86 TDI 87 TDO 88 TRS
~ ~
ITT10943
Figure 21 Table 21 No. 80 81 82 83 84 85 86 87 88
JTAG Boundary Scan Timing JTAG Boundary Scan Timing Parameter Values
Parameter TCK period TCK high time TCK low time TMS setup time TMS hold time TDI setup time TDI hold time TDO valid delay TRS active low
Limit Values min. 250 80 80 40 40 40 40 100 200 max.
Unit ns ns ns ns ns ns ns ns ns
Identification Register : 32 bit; Version: 1 H; Part Number: 59H, Manufacturer: 083 H
Data Sheet
104
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
7.4.3
Reset
1 RES
F0008
Figure 22 Table 22 No. 1
1)
Reset Timing Reset Timing Parameter Values Limit Values min. max. s 101) Unit
Parameter RES pulse width low
while MCLK is running
7.4.4 7.4.4.1
Ax BHE
Microprocessor Interface Intel Bus Interface Mode
CS 3 1 RD WR
ITT10975
3A 2
Figure 23
Intel Non-Multiplexed Address Timing
Data Sheet
105
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
Ax BHE 5 4 6 ALE 7 1 CS 3 RD WR
ITT10977
7A
3A
Figure 24
Intel Multiplexed Address Timing
CS 8 RD 12 WR 10 Dx
F0061
9
11
Figure 25
Intel Read Cycle Timing
Data Sheet
106
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
CS 13 WR 12 RD 15 16 D7... D0 (D15... D8)
ITT06471
14
Figure 26 Table 23 No. 1 2 3 3A 4 5 6 7 7A 8 9 10 11 12 13 14
Intel Write Cycle Timing Intel Bus Interface Timing Parameter Values Limit Values min. max. ns ns ns ns ns ns ns ns ns ns ns 75 10 70 80 70 ns ns ns ns ns 15 0 0 0 20 10 30 0 30 80 70 Unit
Parameter Address1) setup time Address hold time CS setup time CS hold time Address stable before ALE inactive Address hold after ALE inactive ALE pulse width Address latch setup time before cmd active ALE to command inactive delay RD pulse width RD control interval Data valid after RD active Data hold after RD inactive WR to RD or RD to WR control interval WR pulse width WR control interval
2)
Data Sheet
107
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics Table 23 No. 15 16
1) 2)
Intel Bus Interface Timing Parameter Values (cont'd) Limit Values min. max. ns ns 30 10 Unit
Parameter Data stable before WR inactive Data hold after WR inactive
Ax refers to address lines A(6:0) Dx refers to data line D(7:0)
7.4.4.2
Motorola Bus Interface Mode
Ax 17 CS 19 RW 20 22 21 23 19A 18
DS 24 Dx
F0062
25
Figure 27
Motorola Read Cycle Timing
Data Sheet
108
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
Ax BLE 17 CS 19 RW 20 22A DS 26 D7... D0 (D15 ... D8)
ITT10974
18
19A
21 23
27
Figure 28 Table 24 No. 17 18 19 19A 20 21 22 22A 23 24 25 26 27
Motorola Write Cycle Timing Motorola Bus Interface Timing Parameter Values Limit Values min. max. ns ns ns ns ns ns ns ns ns 75 10 30 10 ns ns ns ns 15 0 0 0 10 0 80 70 70 Unit
Parameter Address setup time before DS active Address hold after DS inactive CS active before DS active CS hold after DS inactive RW stable before DS active RW hold after DS inactive DS pulse width (read access) DS pulse width (write access) DS control interval Data valid after DS active (read access) Data hold after DS inactive (read access) Data stable before DS active (write access) Data hold after DS inactive (write access)
Data Sheet
109
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
7.4.5
Framer Interface
1 2 TCLK (TPE=0) data change edge TCLK (TPE=1) 4 XDIP, XDIN
F0055
3
5
Figure 29 Table 25 No. 1 2 3 4 5
TCLK Input Timing TCLK Timing Parameter Values Limit Values min. typ. 488 648 40 40 20 20 max. ns ns % % ns ns Unit
Parameter TCLK period E1 (2.048 MHz) TCLK period T1/J1 (1.544 MHz) TCLK high TCLK low XDIP, XDIN setup time XDIP, XDIN hold time
Data Sheet
110
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
1 2 RCLK (RPE=1) data change edge RCLK (RPE=0) 4 RDOP, RDON
F0054
3
5
Figure 30 Table 26 No. 1 2 3 4 5
RCLK Output Timing RCLK Timing Parameter Values Limit Values min. typ. 488 648 40 40 -10 200 max. ns ns % % ns ns Unit
Parameter RCLK period E1 (2.048 MHz) RCLK period T1/J1 (1.544 MHz) RCLK high RCLK low RDOP, RDON setup time RDOP, RDON hold time
Data Sheet
111
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
1 2 3
SYNC
F0056
Figure 31 Table 27 No. 1
SYNC Timing SYNC Timing Parameter Values Limit Values min. typ. 488 648 125 20 20 max. s s ms % % Unit
Parameter SYNC period (SYNC = 2.048 MHz) SYNC period (SYNC = 1.544 MHz) SYNC period (SYNC = 8 kHz)
2 2
SYNC low time SYNC low time
Data Sheet
112
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
1 2 FSC 3 RCLK
F0053
Figure 32 Table 28 No. 1 2 3
FSC Timing FSC Timing Parameter Values Limit Values min. typ. 125 488 648 370 280 max. s ns ns ns ns Unit
Parameter FSC period FSC low time E1 FSC low time T1/J1 RCLK to FSC delay E1 RCLK to FSC delay T1/J1
Data Sheet
113
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
7.4.6 7.4.6.1
Pulse Templates - Transmitter Pulse Template E1
269 ns (244 + 25) 194 ns (244 - 50)
V=100 %
10 % 10 % 20 % 20 %
Nominal Pulse
50 % 244 ns 219 ns (244 - 25)
10 % 10 %
0%
20 %
488 ns (244 + 244)
ITD00573
Figure 33
Data Sheet
E1 Pulse Shape at Transmitter Output
114 2001-02
10 % 10 %
PEB 22504 QuadLIU V1.1
Electrical Characteristics
7.4.6.2
Pulse Template T1
Normalized Amplitude
V = 100 %
50 %
0
-50 % 0 250 500 750 1000 ns
ITD00574
t
Figure 34
T1 Pulse Shape
Table 29
T1 Pulse Template (ANSI T1.102) Maximum Curve Minimum Curve
1)
Time [ns] 0 250 325 325 425 500 675 725 1100 1250
Level [%] 5 5 80 115 115 105 105 -7 5 5
Time [ns] 0 350 350 400 500 600 650 650 800 925 1100 1250
Level [%] -5 -5 50 95 95 90 50 -45 -45 -20 -5 -5
1)
100 % value must be in the range of 2.4 V and 3.6 V; tested at 0 ft and 655 ft using PIC 22AWG cable characteristics.
Data Sheet
115
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
7.5
Table 30 Parameter
Capacitances
Pin Capacitances Symbol
1)
Limit Values min. max. 10 15 20 5 8 8
Unit Notes pF pF pF all except XLx.y XLx.y
Input capacitance
CIN COUT COUT
1)
Output capacitance1) Output capacitance
1)
not tested in production
7.6
Package Characteristics
F0051
Figure 35 Table 31 Parameter
Thermal Behaviour of Package Package Characteristic Values Symbol Rth Limit Values min. typ. 44 36 32 max. K/W single layer PCB, no convection K/W air flow 200 LFPM K/W air flow 500 LFPM 125 C Unit Notes
Thermal resistance1)
Junction temperature
1)
Rj
Rth = (Tjunction - Tambient)/Power Not tested in production.
Data Sheet
116
2001-02
PEB 22504 QuadLIU V1.1
Electrical Characteristics
7.7
Test Configuration
Test Levels
VTH VTL Timing Test Points Device under Test CL
Drive Levels
VIH VIL F0067
Figure 36 Table 32 Parameter
Input/Output Waveforms for AC Testing AC Test Conditions Symbol CL VIH VIL VTH VTL Test Values 50 2.4 0.4 2.0 0.8 Unit Notes pF V V V V all except RLx.y all except RLx.y all except XLx.y all except XLx.y
Load capacitance Input voltage high Input voltage low Test voltage high Test voltage low
Typical characteristics are mean values expected over the production spread. If not specified otherwise, typical characteristics apply at TA = 25 C and VDD = 3.3V.
Data Sheet
117
2001-02
PEB 22504 QuadLIU V1.1
Package Outlines
8
Package Outlines
P-TQFP-100-3 (Plastic Metric Quad Flat Package)
GPP09189
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device
Data Sheet 118
Dimensions in mm 2001-02
PEB 22504 QuadLIU V1.1
Appendix
9
9.1
Appendix
Application Notes
Online access to supporting information is available on the internet page: http://www.infineon.com/falc On the same page you find as well the * Boundary Scan File for QuadLIUTM Version 1.1 (BSDL File)
9.2
Software Support
The following tool package is provided together with the QuadLIUTM Evaluation System EASY22504: * Flexible Master Clock Calculator * External Line Front End Calculator * IBIS Model for QuadLIUTM V1.1 (according to ANSI/EIA-656) To make system design easier, two software tools are available. The first is the "Master Clock Frequency Calculator", which calculates the required register settings depending on the external master clock frequency (Figure 37). The second is the "External Line Front End Calculator" which provides an easy method to optimize the external components depending on the selected application type. Calculation results are traced and can be stored in a file or printed out for documentation (Figure 38). The tools run under a Windows(R) environment. Screenshots of the programs are shown in the figures below.
Data Sheet
119
2001-02
PEB 22504 QuadLIU V1.1
Appendix
F0126
Figure 37
Master Clock Frequency Calculator
Data Sheet
120
2001-02
PEB 22504 QuadLIU V1.1
Appendix
F0194
Figure 38
External Line Frontend Calculator
Data Sheet
121
2001-02
PEB 22504 QuadLIU V1.1
Glossary
10
A/D ADC AIS AGC ALOS AMI ANSI ATM B8ZS BER Bellcore BPV CVC DCO DL DPLL DS1 ESD EASY EQ ETSI FALC(R) FCC HBM HDB3 IBIS IBL ISDN ITU JATT
Glossary
Analog-to-Digital Analog-to-Digital Converter Alarm Indication Signal (blue alarm) Automatic Gain Control Analog Loss-Of-Signal Alternate Mark Inversion American National Standards Institute Asynchronous Transfer Mode Line coding to avoid too long strings of consecutive '0' Bit Error Rate BELL COmmunications REsearch (see: Telcordia) BiPolar Violation Code Violation Counter Digitally Controlled Oscillator Digital Loop Digitally controlled Phase-Locked Loop Digital Signal level 1 ElectroStatic Discharge EvAluation SYstem for FALC/LIU products EQualizer European Telecommunication Standards Institute Framing And Line interface Component US Federal Communication Commission Human Body Model for ESD classification High-Density Bipolar of order 3 I/O Buffer Information Specification (ANSI/EIA-656) In Band Loop (=LLB) Intergrated sevices digital network International Telecommunications Union Jitter ATTenuator
Data Sheet
122
2001-02
PEB 22504 QuadLIU V1.1
Glossary JTAG LBO LCV LIU LL LLB LOS LSB MSB NRZ PDV PLL PRBS P-TQFP RAI RL Sidactor TAP Telcordia UI Joined Test Action Group Line Build Out Line Code Violation Line Interface Unit Local Loop Line Loop Back (= IBL) Loss-Of-Signal (red alarm) Least Significant Bit Most Significant Bit Non Return to Zero signal Pulse-Density Violation Phase-Locked Loop Pseudo Ramdom Binary Sequence Plastic Thin metric Quad Flat Pack (device package) Remote Alarm Indication (yellow alarm) Remote Loop Overvoltage protection device for transmission lines Test Access Port New organization name, former 'Bellcore' Unit Interval
Data Sheet
123
2001-02
PEB 22504 QuadLIU V1.1
Index A
ACS 46, 70 AIS 39, 89, 93 AISM 82 Alarm Handling 39 Alarm Simulation 54 ANSI T1.102 47 ANSI T1.231 13, 39, 71, 89, 90 ANSI T1.403 13, 39, 47, 50, 67, 89, 90 ANSI/EIA-656 119 Application Notes 119 Applications 16 ARL 50, 62
DSS0 72 DSS1 72
E
EASY22504 119 ECM 64 ECMIR 64 ECMIX 64 ELT 72 EPRM 67 EQON 64 Equalizer 37 Error Counter 49 ESD 98 ETS 300011 13 ETS 300233 13, 39, 40, 89 EV 92 External Line Front End Calculator 119 EXZD 89 EXZE 62
B
Blue Alarm 39 Boundary Scan 33, 104, 119 Buffer 44
C
CEB 83 CIS 30 Clock and Data Recovery 38 Clock Mode Register Settings 87 Clocking Modes 41 Clocking Unit 35 CMDR 83 CMR 72 CV 96
F
FCC Part68 67 Flexible Clock Mode Settings 87 Flexible Master Clock 119 FSC0 60 FSC1 60
G
gapped clocks 40 GCM1 84 GCM2 84 GCM3 85 GCM4 85 GCM5 86 GCM6 86 GCR 60, 61 GCR2 61 GIS 95 GTP 67
D
Data Strobe 19 DBEC 83 DCF 68 DCO 40, 41 DCS 72 DCVC 83 Digital Loop 53 DLB 53 DSS 72
I
IBIS Model 119
124 2001-02
Data Sheet
PEB 22504 QuadLIU V1.1
IBV 83 IC 61 IEEE 1149.1 14, 33 IMR0 82 IMR1 82 In-Band Loop 50 Initialization in E1 Mode 56 INT 30 Interrupt Interface 30 IPE 83 IPRBS 67 ITU-T G.703 40 ITU-T G.735 42 ITU-T G.736 13, 40 ITU-T G.775 13, 39, 89 ITU-T G.823 13, 40 ITU-T I.431 13, 40, 42, 47 ITU-T O.151 49, 68
LL 52 LLBAD 89 LLBDD 89 LLBSC 93 LLBSCM 82 Local Loop 52 Long Haul 36 LOOP 74 loop down 50 loop up 50 LOS 89, 93, 102 LOSM 82 LOSR0 70 LOSR1 70 Loss-of-Signal 39 LTC 94 LTCM 82
J
JATT 40 Jitter 40 Jitter Attenuator 40 Jitter Tolerance 43
M
MAS 72 Master Clock Range 86 MCLK_ LOW 86 Microprocessor Interface 30, 105 MIL-Std 883D 98 MTP 67
L
LAC 81 LACL 80 LBO1 67 LBO2 67 LCR1 80 LCR2 81 LCR3 81 LDC 81 LDCL 80 LIM0 62 LIM1 64 LIM2 66 LIM3 67 LIM4 68 LIM5 70 Line Build-Out 47 Line Coding 38
Data Sheet
O
One-Second Timer 49 Output Jitter 44
P
Payload Loop Back 54 PC0 68 PC1 68 PC2 68 PCD 79 PCR 79 PD 64 PDE 46, 62 PDEN 39, 89 PDENI 93 PMOD 61 P-MQFP-80-1 118
125 2001-02
PEB 22504 QuadLIU V1.1
PRBSS 89 PRBSSC 93 PRBSSCM 82 Pseudo-Random Bit Sequence 49 Pulse Density 39, 46 Pulse Shaper 47 Pulse Template 114, 115
R
R1S0 60 R1S1 60 RC0 62 RC1 62 RD0 66 RD1 66 RDON0 64 RDON1 64 Read/Write Enable 20 Receive Equalization Network 37 Receive Line Attenuation Indication 37 Receive Line Interface 36 Receiver Configuration 36, 45 Red Alarm 39 Register Addresses 59, 88 Remote Loop 51 RES 83 Reset 56, 105 RIL0 66 RIL1 66 RIL2 66 RLS 89 RPE 68 RS0 72 RS1 72
SLN 93 SLNM 82 SLP 93 SLPM 82 SLT0 66 SLT1 66 SPRBS 67 SSF0 60 SSF1 60 Status Register 88 Supply voltage 99
T
TBR12 13, 40, 42 TBR13 13, 40, 42 TCS 91 Test Access Port 33 TPE 46, 68 TR43802 40 TR62411 13, 14, 40, 49 Transmit Clock 46 Transmit Data Monitoring 55 Transmit Line Interface 45 Transmit Line Monitor 48 Transmit Pulse Mask 76 TR-WT-499 89
V
Version Number 97 Version Status Register 97 VFREQ_EN 84 VIS 68 VN 97
S
SCF 72 SCI 68 SEC 94 SECM 82 Short Haul 36 SIM 62 Single Channel Loop Back 54
Data Sheet
W
Wander 40
X
XAIS 64 XC0 62 XC1 62 XDPM 70 XLA 80
126 2001-02
PEB 22504 QuadLIU V1.1
XLB 70 XLD 80 XLM 70 XLO 91 XLS 91 XLSC 93 XLSCM 82 XPM0 76 XPM1 76 XPM2 76 XPRBS 67
Data Sheet
127
2001-02
Total Quality Management
Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced.
http://www.infineon.com
Published by Infineon Technologies AG


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